You can customize port names and set attributes of the external component when you generate an interface from the following blocks:
Model with black box implementation
Subsystem with black box implementation
HDL Cosimulation
Open the HDL Block Properties dialog box to see the interface generation parameters.
The following table summarizes the names, value settings, and purpose of the interface generation parameters.
| Parameter Name | Values | Description |
|---|---|---|
| AddClockEnablePort |
Default: | If on, add a clock enable input
port to the interface generated for the block. The name of the port
is specified by ClockEnableInputPort. |
| AddClockPort |
Default: | If on, add a clock input port to
the interface generated for the block. The name of the port is specified
by ClockInputPort. |
| AddResetPort |
Default: | If on, add a reset input port to
the interface generated for the block. The name of the port is specified
by ResetInputPort. |
| AllowDistributedPipelining |
Default: | If on, allow HDL Coder™ to move
registers across the block, from input to output or output to input. |
| ClockEnableInputPort | Default: | Specifies HDL name for block's clock enable input port. |
| ClockInputPort | Default: | Specifies HDL name for block's clock input signal. |
| EntityName | Default: Entity name string is derived from the block name, and modified when necessary to generate a legal VHDL® entity name. | Specifies VHDLentity or Verilog®module name
generated for the block. |
| GenericList | Pass a cell array variable that contains cell arrays
each with two or three strings, or enter a cell array of cell arrays
that each contain two or three strings. The strings represent the
name, value, and optional data type of a VHDL Default: none | Specifies a list of VHDL For
example, in the HDL Block Properties dialog box, enter To
set
If
the data type is
|
| ImplementationLatency | -1 | 0 | positive integer Default: -1 | Specifies the additional latency of the external component in time steps, relative to the Simulink® block. If 0 or greater, this value is used for delay balancing. Your inputs and outputs must operate at the same rate. If -1, latency is unknown. This disables delay balancing. |
| InlineConfigurations (VHDL only) |
Default:
If this parameter is unspecified, defaults to the value of the global | If off, suppress generation of a
configuration for the block, and require a user-supplied external
configuration. |
| InputPipeline | Default: 0 | Specifies the number of input pipeline stages (pipeline depth) in the generated code. |
| OutputPipeline | Default: 0 | Specifies the number of output pipeline stages (pipeline depth) in the generated code. |
| ResetInputPort | Default: | Specifies HDL name for block's reset input. |
| VHDLArchitectureName (VHDL only) | Default: | Specifies RTL architecture name generated for the block. The
architecture name is generated only if InlineConfigurations is on. |
| VHDLComponentLibrary (VHDL only) | Default: | Specifies the library from which to load the VHDL component. |