To prepare your Simulink® model for code generation:
To check your model for compatibility with HDL code
generation, use the checkhdl function.
When you create the model, you can save time by using a filtered
view in the Library Browser that shows only blocks that are compatible
with HDL code generation. To show this filtered view, use the hdllib command.
Code generation does not support all
available combinations of supported blocks, block implementations,
block properties, and HDL optimizations. The checkhdl function can find many code
generation incompatibilities. However, you can modify your model later
to generate code that meets your hardware requirements.
If you want to synthesize your generated HDL code, convert your model to fixed point.
To learn how to use Fixed-Point Designer™ to convert your floating-point model to a fixed-point model, see Convert Floating-Point Model to Fixed Point.
If your synthesis tool and hardware support floating-point constructs, you can synthesize some of those constructs. To learn more, see FPGA Floating-Point Libraries.
To configure the solver for HDL code generation, run hdlsetup .