Documentation

When To Use Trigger As Clock

Using the trigger as clock in triggered subsystems enables you to partition your design into different clock regions in the generated code.

For example, you can model:

• A design with clocks that run at the same rate, but out of phase.

• Clock regions driven by an external or internal clock divider.

• Clock regions driven by clocks whose rates are not integer multiples of each other.

• Internally generated clocks.

• Clock gating for low-power design.

Requirements For Using Trigger As Clock

Each triggered subsystem input or output data signal must have delays immediately outside and immediately inside the subsystem. These delays act as a synchronization interface between the regions running at different rates.

How To Specify Trigger As Clock

Using the Configuration Parameters Dialog Box

In HDL Code Generation > Global Settings > Optimization tab, select Use trigger signal as clock.

Using the HDL Workflow Advisor

In the HDL Code Generation > Set Code Generation Options > Set Advanced Options > Optimization tab, select Use trigger signal as clock.

At the Command Line

Set the TriggerAsClock property using makehdl or hdlset_param.

For example, to generate HDL code that uses the trigger signal as clock for triggered subsystems in a DUT subsystem, myDUT, in a model, myModel, enter:

makehdl ('myModel/myDUT','TriggerAsClock','on')

Limitations When Using Trigger As Clock

Using the trigger as clock for triggered subsystems can result in timing mismatches of one cycle during testbench simulation.