HDL Coder™ can generate an IP core, integrate it into your EDK project, and program the Zynq hardware. Using Embedded Coder®, you can generate and build the embedded software, and run it on the ARM® processor. See Hardware-Software Co-Design Workflow for SoC Platforms.
hdlcoder.Board |
Board registration object that describes SoC custom board |
hdlcoder.ReferenceDesign |
Reference design registration object that describes SoC reference design |
Hardware-Software Co-Design Workflow for SoC Platforms
High-level workflow steps for targeting an SoC platform
Model Design for AXI4-Stream Interface Generation
How to design your model for AXI4-Stream vector or scalar interface generation
Model Design for AXI4-Stream Video Interface Generation
How to design your model for IP core generation with AXI4-stream video interfaces
Using the HDL Workflow Advisor, you can generate a custom IP core from a model or algorithm.
You generate an HTML custom IP core report by default when you generate a custom IP core.
Processor and FPGA Synchronization
In the HDL Workflow Advisor, you can choose a Processor/FPGA synchronization mode for your processor and FPGA when you:The following synchronization modes are available:
Save Target Hardware Settings in Model
This example shows how to save your target hardware settings in a Simulink® model.
Define the interface and attributes of a custom SoC board. After defining the board, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Register a Custom Reference Design
Define the interface and attributes of a custom SoC reference design. After defining and registering the reference design, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Board and Reference Design Registration System
System for defining and registering boards and reference designs
Define Custom Parameters and Callback Functions for Custom Reference Design
Learn how to define custom parameters and custom callback functions for your custom reference design.
MATLAB Hardware-Software Co-Design for Xilinx Zynq-7000 Platform
Hardware and software co-design workflow example for Xilinx Zynq-7000 platform
Simulink Hardware-Software Co-Design for Xilinx Zynq-7000 Platform
Hardware-software co-design workflow example for Xilinx Zynq-7000 platform
Getting Started with AXI4-Stream Interface in Zynq Workflow
This example shows how to use the AXI4-Stream interface to enable high speed data transfer between the processor and FPGA on Zynq hardware.
Generate a Board-Independent IP Core from Simulink
To generate a board-independent custom IP core to use in an embedded system integration environment, such as Altera® Qsys, Xilinx EDK, or Xilinx IP Integrator:To learn more about custom IP core generation, see Custom IP Core Generation.
Generate a Board-Independent IP Core from MATLAB
Board-independent IP core generation from MATLAB®