Documentation

Generate a Board-Independent IP Core

To generate a board-independent custom IP core to use in an embedded system integration environment, such as Altera^® Qsys, Xilinx^® EDK, or Xilinx IP Integrator:

1. Select your DUT in your Simulink^® model and open the HDL Workflow Advisor.

2. In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select IP Core Generation.

3. For Target platform, select Generic Altera Platform or Generic Xilinx Platform and click Run This Task.

   

4. In the Set Target > Set Target Interface task, select a Target Platform Interface for each port, then click Apply.

   You can map each DUT port to one of the following interfaces:

   • AXI4-Lite: Use this slave interface to access control registers or for lightweight data transfer. HDL Coder™ generates memory-mapped registers and allocates address offsets for the ports you map to this interface.

   • AXI4: Use this slave interface to connect to components that support burst data transmission. HDL Coder generates memory-mapped registers and allocates address offsets for the ports you map to this interface.

   • AXI4-Stream: Use this interface to send or receive a 32-bit scalar data stream.

   • AXI4-Stream Video: Use this interface to send or receive a 32-bit scalar video data stream.

   • External Port: Use the external ports to connect to FPGA external IO pins, or to other IP cores with external ports.

   

5. If you want to set options in the other HDL Workflow Advisor tasks, set them.

6. In the HDL Code Generation > Generate RTL Code and IP Core task, set the following fields:

   • IP repository: If you have an IP repository folder, enter its path manually or by using the Browse button. The coder copies the generated IP core into the IP repository folder.

   • Additional source files: If you are using a black box interface in your design to include existing Verilog^® or VHDL^® code, enter the file names. Enter each file name manually, separated with a semicolon (;), or by using the Add button. The source file language must match your target language.

   • Generate IP core report: Enable this option to generate HTML documentation for the IP core.

7. Right-click the HDL Code Generation > Generate RTL Code and IP Core task and select Run to Selected Task.

   HDL Coder generates the IP core files in the output folder shown the IP core folder field, including the HTML documentation.

   To view the IP core report, click the link in the message window.

To learn more about custom IP core generation, see Custom IP Core Generation.

Requirements and Limitations for IP Core Generation

To generate a custom IP core:

• The DUT must be an atomic system.

• There cannot be both an AXI4 interface and AXI4-Lite interface in the same IP core.

• The DUT cannot contain Xilinx System Generator blocks or Altera DSP Builder Advanced blocks.

• If your target language is VHDL, and your synthesis tool is Xilinx ISE or Altera Quartus II, the DUT cannot contain a model reference.

To map your DUT ports to an AXI4-Lite interface, the input and output ports must:

• Have a bit width less than or equal to 32 bits.

• Be scalar.

When mapping your DUT ports to an AXI4-Stream Video interface, the following requirements and limitations apply:

• Ports must have a 32-bit width.

• Ports must be scalar.

• The model must be single rate.

• You can have a maximum of one input video port and one output video port.

• Your synthesis tool must be Xilinx ISE.

The AXI4-Stream Video interface is not supported in Coprocessing – blocking processor/FPGA synchronization mode.