You can generate an FPGA programming file and Simulink Real-Time FPGA I/O interface for deployment on a Speedgoat board. See IP Core Generation Workflow for Speedgoat Boards.
Generate Simulink Real-Time Interface for Speedgoat Boards
How select and run an automated code generation and synthesis workflow for a Speedgoat target device
Save Target Hardware Settings in Model
This example shows how to save your target hardware settings in a Simulink® model.
IP Core Generation Workflow for Speedgoat Boards
Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design.
Hardware-Software Co-Design Workflow
Hardware-software co-design workflow overview.
Processor and FPGA Synchronization
In the HDL Workflow Advisor, you can choose a Processor/FPGA synchronization mode for your processor and FPGA when you:The following synchronization modes are available: