To deploy your design on a standalone Altera or Xilinx FPGA board, you must install the HDL Coder™ Support Package for Altera FPGA Boards or the HDL Coder Support Package for Xilinx FPGA Boards respectively. For installation information, see HDL Coder Supported Hardware
hdlcoder.Board |
Board registration object that describes SoC custom board |
hdlcoder.ReferenceDesign |
Reference design registration object that describes SoC reference design |
IP Core Generation Workflow for Standalone FPGA Devices
Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design.
Using the HDL Workflow Advisor, you can generate a custom IP core from a model or algorithm.
You generate an HTML custom IP core report by default when you generate a custom IP core.
Save Target Hardware Settings in Model
This example shows how to save your target hardware settings in a Simulink® model.
Define the interface and attributes of a custom SoC board. After defining the board, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Register a Custom Reference Design
Define the interface and attributes of a custom SoC reference design. After defining and registering the reference design, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Board and Reference Design Registration System
System for defining and registering boards and reference designs
Using IP Core Generation Workflow with Xilinx FPGA Boards: Xilinx Kintex-7 KC705
This example shows how to use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Xilinx® parts without an embedded ARM® processor present, but which still utilize the HDL Coder™ generated AXI interface to control the DUT.