Documentation

Generate a Board-Independent IP Core

To generate a board-independent IP core to use in an embedded system integration environment, such as Altera^® Qsys, Xilinx^® EDK, or Xilinx IP Integrator:

1. Create an HDL Coder™ project containing your MATLAB^® design and test bench, or open an existing project.

2. In the HDL Workflow Advisor, define input types and perform fixed-point conversion.

   To learn how to convert your design to fixed-point, see HDL Code Generation from a MATLAB Algorithm.

3. In the HDL Workflow Advisor, in the Select Code Generation Target task:

   • Workflow: Select IP Core Generation.

   • Platform: Select Generic Xilinx Platform or Generic Altera Platform.

     Depending on your selection, the coder automatically sets Synthesis tool. For example, if you select Generic Xilinx Platform, Synthesis tool automatically changes to Xilinx Vivado. You can change the Synthesis tool to Xilinx ISE.

   • Additional source files: If you are using an hdl.BlackBox System object™ to include existing Verilog^® or VHDL^® code, enter the file names. Enter each file name manually, separated with a semicolon (;), or by using the ... button. The source file language must match your target language.

   

4. In the Set Target Interface step, for each port, select an option from the Target Platform Interfaces drop-down list.

   

5. In the HDL Code Generation step, optionally specify code generation options, then click Run.

6. In the HDL Workflow Advisor message pane, click the IP core report link to view detailed documentation for your generated IP core.

Requirements and Limitations for IP Core Generation

You cannot map to both an AXI4 interface and AXI4-Lite interface in the same IP core.

To map your design function inputs or outputs to an AXI4-Lite interface, the input and outputs must:

• Have a bit width less than or equal to 32 bits.

• Be scalar.

When mapping design function inputs or outputs to an AXI4-Stream Video interface, the following requirements apply:

• Ports must have a 32-bit width.

• Ports must be scalar.

• You can have a maximum of one input video port and one output video port.

The AXI4-Stream Video interface is not supported in Coprocessing – blocking processor/FPGA synchronization mode.