| Chart | Implement control logic with finite state machine (HDL Coder) |
| State Transition Table | Represent modal logic in tabular format (HDL Coder) |
| Truth Table | Represent logical decision-making behavior with conditions, decisions, and actions (HDL Coder) |
| Message Viewer | Display message or events between blocks during simulation (HDL Coder) |
Generate HDL for Mealy and Moore Finite State Machines
Considerations for generating HDL code from Mealy and Moore state machines
Design Patterns Using Advanced Chart Features
Design patterns that take advantage of advanced features for efficient HDL code generation
Introduction to Stateflow HDL Code Generation
Introduction and pointers to examples and other information
Hardware Realization of Stateflow Semantics
How chart semantics are represented in generated HDL code; rationale for restrictions on charts that target HDL code generation