Implement control logic with finite state machine (HDL Coder)
The Chart block is available with Stateflow®.
For information about the simulation behavior and block parameters, see Chart.
You can use a tunable parameter in a Stateflow Chart intended for HDL code generation.
For more information, see Generate DUT Ports for Tunable Parameters.
This block has a single, default HDL architecture.
To generate an output port in the HDL code that shows the active state, select Create output port for monitoring in the Properties window of the chart. The output is an enumerated data type. See Use Active State Output Data.
If you want to insert an output register that delays the chart output by a simulation cycle, use the OutputPipeline block property.
Canonical signed digit (CSD) or factored CSD optimization. The
default is none. See also ConstMultiplierOptimization.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Pipeline register distribution, or register retiming. The default
is off. See also DistributedPipelining.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Generate a VHDL® entity or Verilog® module for
each function. The default is off. See
also InstantiateFunctions.
Unroll, stream, or do not optimize loops. The default is none.
See also LoopOptimization.
Map persistent arrays to RAM. The default is off.
See also MapPersistentVarsToRAM.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
Suppress reset logic generation. The default is default,
which generates reset logic. See also ResetType.
Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing.
Generate 2-D matrices in HDL code. The default is off.
See also UseMatrixTypesInHDL.
Warning
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Insert a pipeline register at the output of the specified MATLAB® variable or variables. Specify the list of variables as a character vector, with spaces separating the variables.
This block supports code generation for complex signals.
A chart intended for HDL code generation must be part of a Simulink® subsystem. If the chart for which you want to generate code is at the root level of your model, embed the chart in a subsystem. Connect the relevant signals to the subsystem inputs and outputs.
The current release supports a subset of MATLAB data types in charts intended for use in HDL code generation. Supported data types are
Signed and unsigned integer
Double and single
Note: Some results obtained from HDL code generated for models using double or single data types are not bit-true to results from simulation of the original model. |
Fixed point
Boolean
Enumeration
Note: Except for data types assigned to ports, multidimensional arrays of these types are supported. Port data types must be either scalar or vector. |
You must enable the chart property Execute (enter) Chart at Initialization. This option executes the update chart function immediately following chart initialization. The option is required for HDL because outputs must be available at time 0 (hardware reset). Execution of a Chart at Initialization describes existing restrictions under this property.
The reset action must not entail the delay of combinatorial logic. Therefore, do not perform arithmetic in initialization actions.
To generate HDL code that is more readable and has better synthesis
results, enable the Initialize Outputs Every Time Chart
Wakes Up chart property. If you use a Moore state
machine, HDL Coder™ generates an error if you disable the chart
property.
If you disable Initialize Outputs Every Time Chart Wakes Up, the chart output is persistent, so the generated HDL code must internally register the output values.
A chart intended for HDL code generation must be entirely self-contained. The following restrictions apply:
Do not call MATLAB functions other than min or max.
Do not use MATLAB workspace data.
Do not call C math functions. HDL does not have a counterpart to the C math library.
If the Enable bit operations property
is disabled, do not use the exponentiation operator (^).
The exponentiation operator is implemented with the C Math Library
function pow.
Do not include custom code. Information entered on the Simulation Target > Custom Code pane in the Configuration Parameters dialog box is ignored.
Do not share data (via Data Store Memory blocks) between charts. HDL Coder does not map such global data to HDL because HDL does not support global data.
Stateflow messages are not supported for HDL code generation.
HDL Coder supports the use of input and output events with Stateflow charts, subject to the following constraints:
You can define and use only one input event per Stateflow chart. (There is no restriction on the number of output events that you can use.)
The coder does not support HDL code generation for charts that have a single input event, and which also have nonzero initial values on the chart's output ports.
All input and output events must be edge-triggered.
For detailed information on input and output events, see Activate a Stateflow Chart Using Input Events and Activate a Simulink Block Using Output Events in the Stateflow documentation.
Other than for loops, do not explicitly use
loops in a chart intended for HDL code generation. Observe the following
restrictions on for loops:
The data type of the loop counter variable must be int32.
HDL Coder supports only constant-bounded loops.
The for loop example, sf_for,
shows a design pattern for a for loop using a graphical
function.
HDL Coder imposes additional restrictions on the use of classic chart features. These limitations exist because HDL does not support some features of general-purpose sequential programming languages.
Do not define local events in a chart from which HDL code is generated.
Do not use the following implicit events:
enter
exit
change
You can use the following implicit events:
wakeup
tick
You can use temporal logic if the base events are limited to these types of implicit events.
Note: Absolute-time temporal logic is not supported for HDL code generation. |
Do not use recursion through graphical functions. HDL Coder does not currently support recursion.
Avoid unstructured code. Although charts allow unstructured
code (through transition flow diagrams and graphical functions), this
usage results in goto statements and multiple
function return statements. HDL does not support either goto statements
or multiple function return statements. Therefore, do not use unstructured
flow diagrams.
If you have not selected the Initialize Outputs Every Time Chart Wakes Up chart option, do not read from output ports.
Do not use Data Store Memory objects.
Do not use pointer (&) or indirection
(*) operators. See Pointer and Address Operations.
If a chart gets a run-time overflow error during simulation, it is possible to disable data range error checking and generate HDL code for the chart. However, in such cases, some results obtained from the generated HDL code might not be bit-true to results from the simulation. The recommended practice is to enable overflow checking and eliminate overflow conditions from the model during simulation.