Stateflow® charts provide concise descriptions of complex system behavior using hierarchical finite state machine (FSM) theory, flow diagram notation, and state-transition diagrams.
You use a chart to model a finite state machine or a complex control algorithm intended for realization as an ASIC or FPGA. When the model meets design requirements, you then generate HDL code (VHDL® or Verilog®) that implements the design embodied in the model. You can simulate and synthesize generated HDL code using industry standard tools, and then map your system designs into FPGAs and ASICs.
In general, generation of VHDL or Verilog code from a model containing a chart does not differ greatly from HDL code generation from other models. The HDL code generator is designed to
Support the largest possible subset of chart semantics that is consistent with HDL. This broad subset lets you generate HDL code from existing models without significant remodeling effort.
Generate bit-true, cycle-accurate HDL code that is fully compatible with Stateflow simulation semantics.
When your Simulink® model contains a Stateflow Chart that uses comments, HDL Coder™ generates the comments in the HDL code.
When you generate Verilog code from the model, HDL Coder displays the comments in the Stateflow Chart inline beside the corresponding Stateflow object.
The hdlcodercfir model shows how to generate HDL code for a subsystem that includes Stateflow charts.
To open the model, at the command line, enter:
hdlcodercfir
HDL Coder does not support Stateflow blocks that contain messages for HDL code generation.