Represent logical decision-making behavior with conditions, decisions, and actions (HDL Coder)
The Truth Table block is available with Stateflow®.
For information about the simulation behavior and block parameters, see Truth Table.
You can use a tunable parameter in a Truth Table intended for HDL code generation. For details, see Generate DUT Ports for Tunable Parameters.
This block has a single, default HDL architecture.
Canonical signed digit (CSD) or factored CSD optimization. The
default is none. See also ConstMultiplierOptimization.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Pipeline register distribution, or register retiming. The default
is off. See also DistributedPipelining.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Generate a VHDL® entity or Verilog® module for
each function. The default is off. See
also InstantiateFunctions.
Unroll, stream, or do not optimize loops. The default is none.
See also LoopOptimization.
Map persistent arrays to RAM. The default is off.
See also MapPersistentVarsToRAM.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
Suppress reset logic generation. The default is default,
which generates reset logic. See also ResetType.
Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing.
Generate 2-D matrices in HDL code. The default is off.
See also UseMatrixTypesInHDL.
Warning
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Insert a pipeline register at the output of the specified MATLAB® variable or variables. Specify the list of variables as a character vector, with spaces separating the variables.