Inport

Create input port for subsystem or external input (HDL Coder)

Description

The Inport block is available with Simulink®.

For information about the simulation behavior and block parameters, see Inport.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

General

BidirectionalPort
BidirectionalPort SettingDescription
on

Specify the port as bidirectional.

The following requirements apply:

  • The port must be in a Subsystem block with black box implementation.

  • There must also be no logic between the bidirectional port and the corresponding top-level DUT subsystem port.

For more information, see Specify Bidirectional Ports.

off (default)Do not specify the port as bidirectional.

Target Specification

IOInterface

Target platform interface type for DUT ports, specified as a character vector. The IOInterface block property is ignored for Inport and Outport blocks that are not DUT ports.

To specify valid IOInterface settings, use the HDL Workflow Advisor:

  1. In the HDL Workflow Advisor, in the Set Target > Set Target Interface step, in the Target platform interface table, in the Target Platform Interfaces column, use the drop-down list to set the target platform interface type.

  2. Save the model.

    The IOInterface value is saved as an HDL block property of the port.

    For example, to view the IOInterface value, if the full path to your DUT port is hdlcoder_led_blinking/led_counter/LED, enter:

    hdlget_param('hdlcoder_led_blinking/led_counter/LED', 'IOInterface')

IOInterfaceMapping

Target platform interface port mapping for DUT ports, specified as a character vector. The IOInterfaceMapping block property is ignored for Inport and Outport blocks that are not DUT ports.

To specify valid IOInterfaceMapping settings, use the HDL Workflow Advisor:

  1. In the HDL Workflow Advisor, in the Set Target > Set Target Interface step, in the Target platform interface table, in the Target Platform Interfaces column, use the drop-down list to set the target platform interface type.

  2. In the Bit Range / Address / FPGA Pin column, if you want to change the default value, enter a target platform interface mapping.

  3. Save the model.

    The IOInterfaceMapping value is saved as an HDL block property of the port.

    For example, to view the IOInterfaceMapping value, if the full path to your DUT port is hdlcoder_led_blinking/led_counter/LED, enter:

    hdlget_param('hdlcoder_led_blinking/led_counter/LED',...
             'IOInterfaceMapping')

Related Examples

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