Package: hdlcoder
Configure HDL code generation and deployment workflows
Use the hdlcoder.WorkflowConfig object to set
HDL workflow options for the hdlcoder.runWorkflow function.
You can customize the hdlcoder.WorkflowConfig object
for these workflows:
Generic ASIC/FPGA
FPGA Turnkey
IP core generation
A best practice is to use the HDL Workflow Advisor to configure
the workflow, and then export a workflow script. The commands in the
workflow script create and configure the hdlcoder.WorkflowConfig object.
See Run HDL Workflow with a Script.
hdlcoder.WorkflowConfig( creates
a workflow configuration object for you to specify your HDL code generation
and deployment workflows, with additional options specified by one
or more Name,Value)Name,Value pair arguments.
Specify optional comma-separated pairs of Name,Value arguments.
Name is the argument
name and Value is the corresponding
value. Name must appear
inside single quotes (' ').
You can specify several name and value pair
arguments in any order as Name1,Value1,...,NameN,ValueN.
'SynthesisTool' — Synthesis tool name'Xilinx Vivado' (default) | 'Altera QUARTUS II' | 'Xilinx ISE'Name of the synthesis tool, specified as a character vector.
Example: 'SynthesisTool','Altera QUARTUS II' creates
a workflow configuration object with 'Altera QUARTUS II' as
the synthesis tool and 'Generic ASIC/FPGA' as the
target workflow.
'TargetWorkflow' — Specify the target workflow'Generic ASIC/FPGA' (default) | 'FPGA Turnkey' | 'IP Core Generation'Target workflow for HDL code generation, specified as a character
vector.
Example: 'TargetWorkflow','IP Core Generation' creates
a workflow configuration object with 'Xilinx Vivado' as
the synthesis tool and 'IP Core Generation' as
the target workflow.
ProjectFolder — Folder for generated project files'' (default) | character vectorPath to the folder where your generated project files are saved, specified as a character vector.
Example: 'project_file_folder'
Objective — Synthesis tool objectivehdlcoder.Objective.None (default) | hdlcoder.Objective.SpeedOptimized | hdlcoder.Objective.AreaOptimized | hdlcoder.Objective.CompileOptimizedHigh-level synthesis tool objective, specified as one of these values.
hdlcoder.Objective.None (default) | Do not generate additional Tcl commands. |
hdlcoder.Objective.SpeedOptimized | Generate synthesis tool Tcl commands to optimize for speed. |
hdlcoder.Objective.AreaOptimized | Generate synthesis tool Tcl commands to optimize for area. |
hdlcoder.Objective.CompileOptimized | Generate synthesis tool Tcl commands to optimize for compilation time. |
If your synthesis tool is Xilinx® ISE and your target workflow
is Generic ASIC/FPGA or FPGA Turnkey, set the Objective to hdlcoder.Objective.None.
For the tool-specific Tcl commands that are added to the synthesis project creation Tcl script, see Synthesis Objective to Tcl Command Mapping.
RunTaskGenerateRTLCodeAndTestbench — Enable task to generate code and test benchtrue (default) | falseEnable or disable workflow task to generate code and test bench,
specified as a logical.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.
RunTaskVerifyWithHDLCosimulation — Enable task to verify generated code with HDL cosimulationtrue (default) | falseEnable or disable task to verify the generated code with HDL
cosimulation, specified as a logical. This option
takes effect only when GenerateCosimulationModel is true.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Verify with HDL Cosimulation task.
RunTaskCreateProject — Enable task to create synthesis tool projecttrue (default) | falseEnable or disable task to create a synthesis tool project, specified
as a logical.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Create Project task.
RunTaskPerformLogicSynthesis — Enable task to launch synthesis tool and run logic synthesistrue (default) | falseEnable or disable task to launch the synthesis tool and run
logic synthesis, specified as a logical. This task
is available only when your synthesis tool is Xilinx ISE or Altera® Quartus
II.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Logic Synthesis task.
RunTaskPerformMapping — Enable task to map synthesized logic to target devicetrue (default) | falseEnable or disable task to map the synthesized logic to the target
device, specified as a logical. This task is available
only when your synthesis tool is Xilinx ISE or Altera Quartus
II.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.
RunTaskPerformPlaceAndRoute — Enable task to run place and route processtrue (default) | falseEnable or disable task to run the place and route process, specified
as a logical. This task is available only when
your synthesis tool is Xilinx ISE or Altera Quartus II.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and Route task.
RunTaskRunSynthesis — Enable task to launch Xilinx Vivado® and run synthesistrue (default) | falseEnable or disable task to launch Xilinx Vivado and
run synthesis, specified as a logical. This task
is available only when your synthesis tool is Xilinx Vivado.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Run Synthesis task.
RunTaskRunImplementation — Enable task to launch Xilinx Vivado and run implementationtrue (default) | falseEnable or disable task to launch Xilinx Vivado and
run the implementation step, specified as a logical.
This task is available only when your synthesis tool is Xilinx Vivado.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Run Implementation task.
RunTaskAnnotateModelWithSynthesisResult — Enable task to analyze timing information and highlight critical pathstrue (default) | falseEnable or disable task to analyze pre- or post-routing timing
information and highlight critical paths in your model, specified
as a logical. This task is available only when
the target workflow is Generic ASIC/FPGA.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.
GenerateRTLCode — Generate HDL codetrue (default) | falseOption to generate HDL code in the target language, specified
as a logical.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.
GenerateRTLTestbench — Generate HDL test benchfalse (default) | trueOption to generate an HDL test bench in the target language,
specified as a logical.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.
GenerateCosimulationModel — Generate cosimulation modelfalse (default) | trueOption to generate a cosimulation model, specified as a logical.
This option requires an HDL Verifier™ license.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.
CosimulationModelForUseWith — Cosimulation toolMentor Graphics ModelSim (default) | Cadence IncisiveCosimulation tool, specified as a character vector. When GenerateCosimulationModel is true,
this option is available.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.
GenerateValidationModel — Generate validation modelfalse (default) | trueGenerate a validation model, specified as a logical.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.
AdditionalProjectCreationTclFiles — Additional project creation Tcl files to include in your synthesis project'' (default) | character vectorAdditional project creation Tcl files that you want to include in your synthesis project, specified as a character vector.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Create Project task.
Example: 'L:\file1.tcl;L:\file2.tcl;'
SkipPreRouteTimingAnalysis — Skip pre-route timing analysis logicalfalse (default) | trueSkip pre-route timing analysis, specified as a logical.
If your tool does not support early timing estimation, set to true.
When you enable this option, CriticalPathSource is
set to 'post-route'
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.
IgnorePlaceAndRouteErrors — Ignore place and route errorsfalse (default) | trueIgnore place and route errors, specified as a logical.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and route task.
CriticalPathSource — Critical path source'pre-route' (default) | 'post-route'Critical path source, specified as a character vector.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.
CriticalPathNumber — Number of critical paths to annotateNumber of critical paths to annotate, specified as a positive integer from 1 to 3.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.
ShowAllPaths — Show all critical pathsfalse (default) | trueShow all critical paths, including
duplicate paths, specified as a logical.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.
ShowDelayData — Annotate cumulative timing delay on each critical pathtrue (default) | falseAnnotate the cumulative timing delay on each critical path,
specified as a logical.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.
ShowUniquePaths — Show only the first instance of a critical pathfalse (default) | trueShow only the first instance of a critical path that is duplicated,
specified as a logical.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.
ShowEndsOnly — Show only endpoints of each critical pathfalse (default) | trueShow the endpoints of each critical path, omitting connecting
signal lines, specified as a logical.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.
ProjectFolder — Folder for generated project files'' (default) | character vectorPath to the folder where your generated project files are saved, specified as a character vector.
Example: 'project_file_folder'
Objective — Synthesis tool objectivehdlcoder.Objective.None (default) | hdlcoder.Objective.SpeedOptimized | hdlcoder.Objective.AreaOptimized | hdlcoder.Objective.CompileOptimizedHigh-level synthesis tool objective, specified as one of these values.
hdlcoder.Objective.None (default) | Do not generate additional Tcl commands. |
hdlcoder.Objective.SpeedOptimized | Generate synthesis tool Tcl commands to optimize for speed. |
hdlcoder.Objective.AreaOptimized | Generate synthesis tool Tcl commands to optimize for area. |
hdlcoder.Objective.CompileOptimized | Generate synthesis tool Tcl commands to optimize for compilation time. |
If your synthesis tool is Xilinx ISE and your target workflow
is Generic ASIC/FPGA or FPGA Turnkey, set the Objective to hdlcoder.Objective.None.
For the tool-specific Tcl commands that are added to the synthesis project creation Tcl script, see Synthesis Objective to Tcl Command Mapping.
RunTaskGenerateRTLCode — Enable task to generate RTL code and HDL top-level wrappertrue (default) | falseEnable or disable workflow task to generate RTL code and an
HDL top-level wrapper, specified as a logical.
When enabled, this task also generates a constraint file that contains
pin mapping information and clock constraints.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code task.
RunTaskCreateProject — Enable task to create synthesis tool projecttrue (default) | falseEnable or disable task to create a synthesis tool project, specified
as a logical.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Create Project task.
RunTaskPerformLogicSynthesis — Enable task to launch synthesis tool and run logic synthesistrue (default) | falseEnable or disable task to launch the synthesis tool and run
logic synthesis, specified as a logical. This task
is available only when your synthesis tool is Xilinx ISE or Altera Quartus
II.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Logic Synthesis task.
RunTaskPerformMapping — Enable task to map synthesized logic to target devicetrue (default) | falseEnable or disable task to map the synthesized logic to the target
device, specified as a logical. This task is available
only when your synthesis tool is Xilinx ISE or Altera Quartus
II.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.
RunTaskPerformPlaceAndRoute — Enable task to run place and route processtrue (default) | falseEnable or disable task to run the place and route process, specified
as a logical. This task is available only when
your synthesis tool is Xilinx ISE or Altera Quartus II.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and Route task.
RunTaskRunSynthesis — Enable task to launch Xilinx Vivado and run synthesistrue (default) | falseEnable or disable task to launch Xilinx Vivado and
run synthesis, specified as a logical. This task
is available only when your synthesis tool is Xilinx Vivado.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Run Synthesis task.
RunTaskRunImplementation — Enable task to launch Xilinx Vivado and run implementationtrue (default) | falseEnable or disable task to launch Xilinx Vivado and
run the implementation step, specified as a logical.
This task is available only when your synthesis tool is Xilinx Vivado.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Run Implementation task.
RunTaskGenerateProgrammingFile — Enable task to generate FPGA programming filetrue (default) | falseEnable or disable task to generate an FPGA programming file,
specified as a logical. This task is available
only when the target workflow is FPGA Turnkey.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Download to Target > Generate Programming File task.
RunTaskProgramTargetDevice — Enable task to program target devicetrue (default) | falseEnable or disable task to download the FPGA programming file
to the target device, specified as a logical. This
task is available only when the target workflow is FPGA Turnkey.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Download to Target > Program Target Device task.
AdditionalProjectCreationTclFiles — Additional project creation Tcl files to include in your synthesis project'' (default) | character vectorAdditional project creation Tcl files that you want to include in your synthesis project, specified as a character vector.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Create Project task.
Example: 'L:\file1.tcl;L:\file2.tcl;'
SkipPreRouteTimingAnalysis — Skip pre-route timing analysis logicalfalse (default) | trueSkip pre-route timing analysis, specified as a logical.
If your tool does not support early timing estimation, set to true.
When this option is enabled, CriticalPathSource is
set to 'post-route'
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.
IgnorePlaceAndRouteErrors — Ignore place and route errorsfalse (default) | trueIgnore place and route errors, specified as a logical.
In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and route task.
ProjectFolder — Folder for generated project files'' (default) | character vectorPath to the folder where your generated project files are saved, specified as a character vector.
Example: 'project_file_folder'
RunTaskGenerateRTLCodeAndIPCore — Enable task to generate code and IP coretrue (default) | falseEnable or disable workflow task to generate code and IP core
for embedded system, specified as a logical.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and IP Core task.
RunTaskCreateProject — Enable task to create embedded system tool projecttrue (default) | falseEnable or disable workflow task to create an embedded system
tool project, specified as a logical.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Create Project task.
RunTaskGenerateSoftwareInterfaceModel — Enable task to generate software interface modeltrue (default) | falseEnable or disable workflow task to generate a software interface
model with IP core driver blocks for embedded C code generation, specified
as a logical.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Generate Software Interface Model task.
RunTaskBuildFPGABitstream — Enable task to generate bitstream for embedded systemtrue (default) | falseEnable or disable workflow task to generate a bitstream for
the embedded system, specified as a logical.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Build FPGA Bitstream task.
RunTaskProgramTargetDevice — Enable task to program connected target devicefalse (default) | trueEnable or disable workflow task to program the connected target
device, specified as a logical.
In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Program Target Device task.
IPCoreRepository — IP core repository folder path'' (default) | character vectorFull path to an IP core repository folder, specified as a character vector. The coder copies the generated IP core into the IP repository folder.
Example: 'L:\sandbox\work\IPfolder'
GenerateIPCoreReport — Generate HTML documentation for the IP coretrue (default) | falseOption to generate HTML documentation for the IP core, specified
as a logical. For details, see Custom IP Core Report.
Objective — Synthesis tool objectivehdlcoder.Objective.None (default) | hdlcoder.Objective.SpeedOptimized | hdlcoder.Objective.AreaOptimized | hdlcoder.Objective.CompileOptimizedHigh-level synthesis tool objective, specified as one of these values.
hdlcoder.Objective.None (default) | Do not generate additional Tcl commands. |
hdlcoder.Objective.SpeedOptimized | Generate synthesis tool Tcl commands to optimize for speed. |
hdlcoder.Objective.AreaOptimized | Generate synthesis tool Tcl commands to optimize for area. |
hdlcoder.Objective.CompileOptimized | Generate synthesis tool Tcl commands to optimize for compilation time. |
If your synthesis tool is Xilinx ISE and your target workflow
is Generic ASIC/FPGA or FPGA Turnkey, set the Objective to hdlcoder.Objective.None.
For the tool-specific Tcl commands that are added to the synthesis project creation Tcl script, see Synthesis Objective to Tcl Command Mapping.
OperatingSystem — Operating system'' (default) | character vectorOperating system for embedded processor, specified as a character vector. The operating system is board-specific.
AddLinuxDeviceDriver — Add IP core device driverfalse (default) | trueOption to insert the IP core node into the operating system
device tree on the SD card on your board, specified as a logical.
This option also restarts the operating system and adds the IP core
driver as a loadable kernel module.
To use this option, your board must be connected.
RunExternalBuild — Run build process externallytrue (default) | falseOption to run build process in parallel with MATLAB®, specified
as a logical. If this option is disabled, you cannot
use MATLAB until the build is finished.
TclFileForSynthesisBuild — Use custom or default synthesis tool build scripthdlcoder.BuildOption.Default (default) | hdlcoder.BuildOption.CustomSelect whether to use a custom or default synthesis tool build script, specified as one of these values:
hdlcoder.BuildOption.Default (default) | Use the default build script. |
hdlcoder.BuildOption.Custom | Use a custom build script instead of the default build script. |
CustomBuildTclFile — Custom synthesis tool build script file'' (default) | character vectorFull path to a custom synthesis tool build Tcl script file,
specified as a character vector. The contents of your custom Tcl file
are inserted between the Tcl commands that open and close the project.
If TclFileForSynthesisBuild is set to hdlcoder.BuildOption.Custom,
you must specify a file.
If you want to generate a bitstream, the bitstream generation Tcl command must refer to the top file wrapper name and location either directly or implicitly. For example, this Xilinx Vivado Tcl command generates a bitstream and implicitly refers to the top file name and location:
launch_runs impl_1 -to_step write_bitstream
Example: ''L:\sandbox\work\build.tcl'
| clearAllTasks | Disable all tasks in workflow |
| export | Generate MATLAB script that recreates the workflow configuration |
| setAllTasks | Enable all tasks in workflow |
| validate | Check property values in HDL Workflow CLI configuration object |
This example shows how to configure and run an exported HDL workflow script.
To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink® design, then export the script.
This script is a generic ASIC/FPGA workflow script that targets a Xilinx Virtex® 7 device and uses the Xilinx Vivado synthesis tool.
Open and view your exported HDL workflow script.
% Export Workflow Configuration Script % Generated with MATLAB 8.6 (R2015b) at 11:33:25 on 08/07/2015 % Parameter Values: % Filename : 'S:\generic_workflow_example.m' % Overwrite : true % Comments : true % Headers : true % DUT : 'sfir_fixed/symmetric_fir1' %% Load the Model load_system('sfir_fixed'); %% Model HDL Parameters % Set Model HDL parameters hdlset_param('sfir_fixed', 'HDLSubsystem', 'sfir_fixed/symmetric_fir1'); hdlset_param('sfir_fixed', 'SynthesisTool', 'Xilinx Vivado'); hdlset_param('sfir_fixed', 'SynthesisToolChipFamily', 'Virtex7'); hdlset_param('sfir_fixed', 'SynthesisToolDeviceName', 'xc7vx485t'); hdlset_param('sfir_fixed', 'SynthesisToolPackageName', 'ffg1761'); hdlset_param('sfir_fixed', 'SynthesisToolSpeedValue', '-2'); hdlset_param('sfir_fixed', 'TargetDirectory', 'hdl_prj\hdlsrc'); %% Workflow Configuration Settings % Construct the Workflow Configuration Object with default settings hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx Vivado','TargetWorkflow', ... 'Generic ASIC/FPGA'); % Specify the top level project directory hWC.ProjectFolder = 'hdl_prj'; % Set Workflow tasks to run hWC.RunTaskGenerateRTLCodeAndTestbench = true; hWC.RunTaskVerifyWithHDLCosimulation = true; hWC.RunTaskCreateProject = true; hWC.RunTaskRunSynthesis = true; hWC.RunTaskRunImplementation = false; hWC.RunTaskAnnotateModelWithSynthesisResult = true; % Set Properties related to Generate RTL Code And Testbench Task hWC.GenerateRTLCode = true; hWC.GenerateRTLTestbench = false; hWC.GenerateCosimulationModel = false; hWC.CosimulationModelForUseWith = 'Mentor Graphics ModelSim'; hWC.GenerateValidationModel = false; % Set Properties related to Create Project Task hWC.Objective = hdlcoder.Objective.None; hWC.AdditionalProjectCreationTclFiles = ''; % Set Properties related to Run Synthesis Task hWC.SkipPreRouteTimingAnalysis = false; % Set Properties related to Run Implementation Task hWC.IgnorePlaceAndRouteErrors = false; % Set Properties related to Annotate Model With Synthesis Result Task hWC.CriticalPathSource = 'pre-route'; hWC.CriticalPathNumber = 1; hWC.ShowAllPaths = false; hWC.ShowDelayData = true; hWC.ShowUniquePaths = false; hWC.ShowEndsOnly = false; % Validate the Workflow Configuration Object hWC.validate; %% Run the workflow hdlcoder.runWorkflow('sfir_fixed/symmetric_fir1', hWC);
Optionally, edit the script.
For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.
Run the HDL workflow script.
For example, if the script file name is generic_workflow_example.m,
at the command line, enter:
generic_workflow_example.m
This example shows how to configure and run an exported HDL workflow script.
To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.
This script is an FPGA Turnkey workflow script that targets a Xilinx Virtex 5 development board and uses the Xilinx ISE synthesis tool.
Open and view your exported HDL workflow script.
% Export Workflow Configuration Script % Generated with MATLAB 8.6 (R2015b) at 14:24:32 on 08/07/2015 % Parameter Values: % Filename : 'S:\turnkey_workflow_example.m' % Overwrite : true % Comments : true % Headers : true % DUT : 'hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA' %% Load the Model load_system('hdlcoderUARTServoControllerExample'); %% Model HDL Parameters % Set Model HDL parameters hdlset_param('hdlcoderUARTServoControllerExample', ... 'HDLSubsystem', 'hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA'); hdlset_param('hdlcoderUARTServoControllerExample', ... 'SynthesisTool', 'Xilinx ISE'); hdlset_param('hdlcoderUARTServoControllerExample', ... 'SynthesisToolChipFamily', 'Virtex5'); hdlset_param('hdlcoderUARTServoControllerExample', ... 'SynthesisToolDeviceName', 'xc5vsx50t'); hdlset_param('hdlcoderUARTServoControllerExample', ... 'SynthesisToolPackageName', 'ff1136'); hdlset_param('hdlcoderUARTServoControllerExample', ... 'SynthesisToolSpeedValue', '-1'); hdlset_param('hdlcoderUARTServoControllerExample', ... 'TargetDirectory', 'hdl_prj\hdlsrc'); hdlset_param('hdlcoderUARTServoControllerExample', ... 'TargetPlatform', 'Xilinx Virtex-5 ML506 development board'); hdlset_param('hdlcoderUARTServoControllerExample', 'Workflow', 'FPGA Turnkey'); % Set Inport HDL parameters hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/uart_rxd', ... 'IOInterface', 'RS-232 Serial Port Rx'); hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/uart_rxd', ... 'IOInterfaceMapping', '[0]'); % Set Outport HDL parameters hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/uart_txd', ... 'IOInterface', 'RS-232 Serial Port Tx'); hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/uart_txd', ... 'IOInterfaceMapping', '[0]'); % Set Outport HDL parameters hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/version', ... 'IOInterface', 'LEDs General Purpose [0:7]'); hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/version', ... 'IOInterfaceMapping', '[0:3]'); % Set Outport HDL parameters hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/pwm_output', ... 'IOInterface', 'Expansion Headers J6 Pin 2-64 [0:31]'); hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/pwm_output', ... 'IOInterfaceMapping', '[0]'); % Set Outport HDL parameters hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/servo_debug1', ... 'IOInterface', 'Expansion Headers J6 Pin 2-64 [0:31]'); hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/servo_debug1', ... 'IOInterfaceMapping', '[1]'); % Set Outport HDL parameters hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/servo_debug2', ... 'IOInterface', 'Expansion Headers J6 Pin 2-64 [0:31]'); hdlset_param('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA/servo_debug2', ... 'IOInterfaceMapping', '[2]'); %% Workflow Configuration Settings % Construct the Workflow Configuration Object with default settings hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx ISE', ... 'TargetWorkflow','FPGA Turnkey'); % Specify the top level project directory hWC.ProjectFolder = 'hdl_prj'; % Set Workflow tasks to run hWC.RunTaskGenerateRTLCodeAndTestbench = true; hWC.RunTaskVerifyWithHDLCosimulation = true; hWC.RunTaskCreateProject = true; hWC.RunTaskPerformLogicSynthesis = true; hWC.RunTaskPerformMapping = true; hWC.RunTaskPerformPlaceAndRoute = true; hWC.RunTaskGenerateProgrammingFile = true; hWC.RunTaskProgramTargetDevice = false; % Set Properties related to Create Project Task hWC.Objective = hdlcoder.Objective.None; hWC.AdditionalProjectCreationTclFiles = ''; % Set Properties related to Perform Mapping Task hWC.SkipPreRouteTimingAnalysis = true; % Set Properties related to Perform Place and Route Task hWC.IgnorePlaceAndRouteErrors = false; % Validate the Workflow Configuration Object hWC.validate; %% Run the workflow hdlcoder.runWorkflow('hdlcoderUARTServoControllerExample/UART_Servo_on_FPGA', hWC);
Optionally, edit the script.
For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.
Run the HDL workflow script.
For example, if the script file name is turnkey_workflow_example.m,
at the command line, enter:
turnkey_workflow_example.m
This example shows how to configure and run an exported HDL workflow script.
To generate an HDL workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.
This script is an IP core generation workflow script that targets the Altera Cyclone V SoC development kit and uses the Altera Quartus II synthesis tool.
Open and view your exported HDL workflow script.
% Export Workflow Configuration Script % Generated with MATLAB 8.6 (R2015b) at 14:42:16 on 08/07/2015 % Parameter Values: % Filename : 'S:\ip_core_gen_workflow_example.m' % Overwrite : true % Comments : true % Headers : true % DUT : 'hdlcoder_led_blinking/led_counter' %% Load the Model load_system('hdlcoder_led_blinking'); %% Model HDL Parameters % Set Model HDL parameters hdlset_param('hdlcoder_led_blinking', ... 'HDLSubsystem', 'hdlcoder_led_blinking/led_counter'); hdlset_param('hdlcoder_led_blinking', 'OptimizationReport', 'on'); hdlset_param('hdlcoder_led_blinking', ... 'ReferenceDesign', 'Default system (Qsys 14.0)'); hdlset_param('hdlcoder_led_blinking', 'ResetType', 'Synchronous'); hdlset_param('hdlcoder_led_blinking', 'ResourceReport', 'on'); hdlset_param('hdlcoder_led_blinking', 'SynthesisTool', 'Altera QUARTUS II'); hdlset_param('hdlcoder_led_blinking', 'SynthesisToolChipFamily', 'Cyclone V'); hdlset_param('hdlcoder_led_blinking', 'SynthesisToolDeviceName', '5CSXFC6D6F31C6'); hdlset_param('hdlcoder_led_blinking', 'TargetDirectory', 'hdl_prj\hdlsrc'); hdlset_param('hdlcoder_led_blinking', ... 'TargetPlatform', 'Altera Cyclone V SoC development kit - Rev.D'); hdlset_param('hdlcoder_led_blinking', 'Traceability', 'on'); hdlset_param('hdlcoder_led_blinking', 'Workflow', 'IP Core Generation'); % Set SubSystem HDL parameters hdlset_param('hdlcoder_led_blinking/led_counter', ... 'ProcessorFPGASynchronization', 'Free running'); % Set Inport HDL parameters hdlset_param('hdlcoder_led_blinking/led_counter/Blink_frequency', ... 'IOInterface', 'AXI4'); hdlset_param('hdlcoder_led_blinking/led_counter/Blink_frequency', ... 'IOInterfaceMapping', 'x"100"'); % Set Inport HDL parameters hdlset_param('hdlcoder_led_blinking/led_counter/Blink_direction', ... 'IOInterface', 'AXI4'); hdlset_param('hdlcoder_led_blinking/led_counter/Blink_direction', ... 'IOInterfaceMapping', 'x"104"'); % Set Outport HDL parameters hdlset_param('hdlcoder_led_blinking/led_counter/LED', 'IOInterface', 'External Port'); % Set Outport HDL parameters hdlset_param('hdlcoder_led_blinking/led_counter/Read_back', 'IOInterface', 'AXI4'); hdlset_param('hdlcoder_led_blinking/led_counter/Read_back', ... 'IOInterfaceMapping', 'x"108"'); %% Workflow Configuration Settings % Construct the Workflow Configuration Object with default settings hWC = hdlcoder.WorkflowConfig('SynthesisTool','Altera QUARTUS II', ... 'TargetWorkflow','IP Core Generation'); % Specify the top level project directory hWC.ProjectFolder = 'hdl_prj'; % Set Workflow tasks to run hWC.RunTaskGenerateRTLCodeAndIPCore = true; hWC.RunTaskCreateProject = true; hWC.RunTaskGenerateSoftwareInterfaceModel = false; hWC.RunTaskBuildFPGABitstream = true; hWC.RunTaskProgramTargetDevice = false; % Set Properties related to Generate RTL Code And IP Core Task hWC.IPCoreRepository = ''; hWC.GenerateIPCoreReport = true; % Set Properties related to Create Project Task hWC.Objective = hdlcoder.Objective.AreaOptimized; % Set Properties related to Generate Software Interface Model Task hWC.OperatingSystem = ''; hWC.AddLinuxDeviceDriver = false; % Set Properties related to Build FPGA Bitstream Task hWC.RunExternalBuild = true; hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Default; % Validate the Workflow Configuration Object hWC.validate; %% Run the workflow hdlcoder.runWorkflow('hdlcoder_led_blinking/led_counter', hWC);
Optionally, edit the script.
For example, enable or disable tasks in the hdlcoder.WorkflowConfig object, hWC.
Run the HDL workflow script.
For example, if the script file name is ip_core_workflow_example.m,
at the command line, enter:
ip_core_gen_workflow_example.m