Dual port RAM with single output port (HDL Coder)
The Simple Dual Port RAM block is available with Simulink®.
For information about the simulation behavior and block parameters, see Simple Dual Port RAM.
This block has a single, default HDL architecture.
HDL code generated for RAM blocks has:
A latency of one clock cycle for read data output.
No reset signal, because some synthesis tools do not infer a RAM from HDL code if it includes a reset.
Code generation for a RAM block creates a separate file, blockname.ext. blockname is
derived from the name of the RAM block. ext is
the target language file name extension.
Code generated to initialize a RAM is intended for simulation only. Synthesis tools can ignore this code.
The HDL block property, RAMArchitecture,
enables or suppresses generation of clock enable logic for all
RAM blocks in a subsystem. You can set RAMArchitecture to
the following values:
WithClockEnable (default): Generates
RAM using HDL templates that include a clock enable signal, and an
empty RAM wrapper.
WithoutClockEnable: Generates
RAM without clock enables, and a RAM wrapper that implements the clock
enable logic.
Some synthesis tools do not infer RAM with a clock enable. If
your synthesis tool does not support RAM structures with a clock enable,
and cannot map your generated HDL code to FPGA RAM resources, set RAMArchitecture to WithoutClockEnable.
To learn how to generate RAM without clock enables for your design, see the Getting Started with RAM and ROM example. To open the example, at the command prompt, enter:
hdlcoderramrom
If you use RAM blocks to perform concurrent read and write operations, verify the read-during-write behavior in hardware. The read-during-write behavior of the RAM blocks in Simulink matches that of the generated behavioral HDL code. However, if a synthesis tool does not follow the same behavior during RAM inference, it causes the read-during-write behavior in hardware to differ from the behavior of the Simulink model or generated HDL code.
Your synthesis tool might not map the generated code to RAM for the following reasons:
Small RAM size: your synthesis tool uses registers to implement a small RAM for better performance.
A clock enable signal is present. You can suppress generation of a clock enable signal in RAM blocks, as described in Implement RAM With or Without Clock Enable.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
This block supports code generation for complex signals.