Copy or invert one scalar input, or collapse one nonscalar input (HDL Coder)
The Product of Elements block is available with Simulink®.
For information about the simulation behavior and block parameters, see Product of Elements.
HDL Coder™ supports Tree and Cascade architectures
for Product or Product of Elements blocks that have a single vector
input with multiple elements.
This block has multi-cycle implementations that introduce additional latency in the generated code. To see the added latency, view the generated model or validation model. See Generated Model and Validation Model.
| Architecture | Additional cycles of latency | Description |
|---|---|---|
Linear (default) | 0 | Generates a linear chain of adders to compute the sum of products. |
Tree | 0 | Generates a tree structure of adders to compute the sum of products. |
Cascade | 1, when block has a single vector input port. | This implementation optimizes latency * area and is faster
than the |
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Synthesis attributes for multiplier mapping. The default is none.
See also DSPStyle.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
The default (linear) implementation supports complex data.
Complex division is not supported. For block implementations of the Product block in divide mode or reciprocal mode, see Divide.