Divide one input by another (HDL Coder)
The Divide block is available with Simulink®.
For information about the simulation behavior and block parameters, see Divide.
To perform an HDL-optimized divide operation, connect a Product block to a Divide block in reciprocal mode. For information about the Divide block in reciprocal mode, see Reciprocal Mode.
In default mode, the Divide block supports only integer data types for HDL code generation.
Architecture | Parameters | Description |
---|---|---|
default Linear | None | Generate a divide (/ ) operator in the HDL
code. |
When Number of Inputs is set to /
,
the Divide block is in reciprocal mode.
This block has multi-cycle implementations that introduce additional latency in the generated code. To see the added latency, view the generated model or validation model. See Generated Model and Validation Model.
In reciprocal mode, the Divide block has the HDL block implementations described in the following table.
Architectures | Parameters | Additional cycles of latency | Description |
---|---|---|---|
default Linear | None | 0 | When you compute a reciprocal, use the HDL divide ( |
ReciprocalRsqrtBasedNewton | Iterations | Signed input: Unsigned
input: | Use the iterative Newton method. Select this option to optimize area. The default value for The recommended value for |
ReciprocalRsqrtBasedNewtonSingleRate | Iterations | Signed input: ( Unsigned input: ( | Use the single rate pipelined Newton method. Select this option to optimize speed, or if you want a single rate implementation. The
default value for The
recommended value for |
The Newton-Raphson iterative method:
ReciprocalRsqrtBasedNewton
and ReciprocalRsqrtBasedNewtonSingleRate
implement
the Newton-Raphson method with:
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Synthesis attributes for multiplier mapping. The default is none
.
See also DSPStyle.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
This block does not support code generation for division with complex signals.
When you use the Divide block in reciprocal mode, the following restrictions apply:
The input must be scalar and must have integer or fixed-point (signed or unsigned) data type.
The output must be scalar and have integer or fixed-point (signed or unsigned) data type.
Only the Zero
rounding
mode is supported.
You must select the Saturate on integer overflow option on the block.