Include model as block in another model (HDL Coder)
The Model block is available with Simulink®. For information about the simulation behavior and block parameters, see Model.
If you enter text in the Model Block Properties dialog box Description field, HDL Coder™ generates a comment in the HDL code.
To generate a single Verilog® module or VHDL® entity for
instances of a referenced model with different model argument values,
see Generate Parameterized Code for Referenced Models.
| Architecture | Description |
|---|---|
ModelReference (default) | When you want to generate code from a referenced model and
any nested models, use the ModelReference implementation.
For more information, see How To Generate Code for a Referenced Model. |
BlackBox | Use the For more information, see Generate Black Box Interface for Referenced Model. |
For the BlackBox architecture, you
can customize port names and set attributes of the external component
interface. See Customize Black Box or HDL Cosimulation Interface.
Detects introduction of new delays along one path, and inserts
matching delays on the other paths. The default is inherit.
See also BalanceDelays.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Pipeline register distribution, or register retiming. The default
is off. See also DistributedPipelining.
Synthesis attributes for multiplier mapping. The default is none.
See also DSPStyle.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing.
Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See also Streaming.
When you generate HDL code for referenced models, the following limitations apply:
You must set the block parameters for the Model block to their default values.
If multiple model references refer to the same model, their HDL block properties must be the same.
Referenced models cannot be protected models.
Hierarchical distributed pipelining must be disabled.
HDL Coder cannot move registers across a model reference. Therefore, referenced models may inhibit the following optimizations:
Distributed pipelining
Constrained output pipelining
The coder cannot apply the streaming optimization to a model reference.
The coder can apply the resource sharing optimization to share referenced model instances. However, you can apply this optimization only when all model references that point to the same referenced model have the same rate after optimizations and rate propagation. The model reference final rate may differ from the original rate, but all model references that point to the same referenced model must have the same final rate.