Speed Optimization

Critical path estimation and reduction, pipeline register insertion, loop unrolling, automated iterative clock frequency optimization

Functions

`hdlcoder.optimizeDesign`	Automatic iterative HDL design optimization
`hdlcoder.supportedDevices`	Show supported target hardware and device details

Properties

SynthesisTool	Specify synthesis tool
SynthesisToolDeviceName	Specify target device name
SynthesisToolChipFamily	Specify target device chip family name
SynthesisToolPackageName	Specify target device package name
SynthesisToolSpeedValue	Specify target device speed value
TargetFrequency	Specify the target frequency for multiple features and workflows

Classes

hdlcoder.OptimizationConfig hdlcoder.optimizeDesign configuration object

Examples and How To

Find Estimated Critical Paths Without Synthesis Tools

Find the estimated critical paths in your design without using synthesis tools

Distributed Pipelining and Hierarchical Distributed Pipelining

Definition, benefits, and costs of distributed pipelining and hierarchical distributed pipelining.

Constrained Output Pipelining

Constrained output pipelining definition and use case.

Reduce Critical Path with Distributed Pipelining

This example shows how to reduce your critical path using distributed pipelining, hierarchical distributed pipelining, output pipelining, and constrained output pipelining.

Insert Distributed Pipeline Registers in a Subsystem

This example shows how to use distributed pipelining with the dct8_fixed model.

Pipeline MATLAB Expressions

Insert registers at output of MATLAB^® expression

Optimize MATLAB Loops

Optimize loops for area or speed.

Find Feedback Loops

Highlight feedback loops that are inhibiting optimizations