| HDL Coder | Generate HDL code from MATLAB code |
codegen |
Generate HDL code from MATLAB code |
coder.config |
Create HDL Coder code generation configuration objects |
hdlcoder.CodingStandard |
Create HDL coding standard customization object |
hdlsetuptoolpath |
Set up system environment to access FPGA synthesis software |
coder.HdlConfig |
HDL codegen configuration object |
hdl.BlackBox |
Black box for including custom HDL code |
| HDL Coding Standard Customization Properties | Customize HDL coding standard |
Basic HDL Code Generation with the Workflow Advisor
This example shows how to work with MATLAB® HDL Coder™ projects to generate HDL from MATLAB designs.
Create and Set Up Your Project
Describes how to open an existing HDL Coder™ project
Generate HDL Code from MATLAB Code Using the Command Line Interface
This example shows how to use the HDL Coder™ command line interface to generate HDL code from MATLAB® code, including floating-point to fixed-point conversion and FPGA programming file generation.
HDL Code Generation from System Objects
This example shows how to generate HDL code from MATLAB® code that contains System objects.
Generate Instantiable Code for Functions
You can use the Generate instantiable code for functions option
to generate a VHDL® entity or Verilog® module for each function.
Integrate Custom HDL Code Into MATLAB Design
Include pre-existing HDL code in your MATLAB® design
Configure clock enable to run at design base rate or input data rate.
Generate code for registers without clock enables
Generate an HDL Coding Standard Report from MATLAB
How to generate a coding standard report for a model
Generate an HDL Lint Tool Script
How to generate lint tool scripts and integrate with third-party tools
Enable MATLAB Function Block Generation
During HDL code generation, your MATLAB algorithm must go through the floating-point to fixed-point conversion process, even if it is already a fixed-point algorithm.
System Design with HDL Code Generation from MATLAB and Simulink
This example shows how to generate a MATLAB Function block from a MATLAB® design for system simulation, code generation, and FPGA programming in Simulink®.
Generate Xilinx System Generator Black Box Block
You must have Xilinx® ISE Design Suite 13.4 or later to generate a System Generator Black Box block.
Generate Xilinx System Generator for DSP Black Box from MATLAB HDL Design
This example shows how to generate a Xilinx ® System Generator for DSP Black Box block from a MATLAB® HDL design.
Generate a Board-Independent IP Core from MATLAB
Board-independent IP core generation from MATLAB
Learn about HDL coding standards and the various kinds of rules.
What is an HDL coding standard report, the rule summary, and how you can fix warnings or errors related to rule violations.
Contains a list of various kinds of rules related to basic coding practices, the rule description, and how you can fix warnings or errors resulting from rule violations.
Contains a list of various kinds of rules related to RTL description techniques, the rule description, and how you can fix warnings or errors resulting from rule violations.
RTL Design Methodology Guidelines
Contains a list of various kinds of rules related to RTL design methodology, the rule description, and how you can fix warnings or errors resulting from rule violations.
Using the HDL Workflow Advisor, you can generate a custom IP core from a model or algorithm.
Overview of the HDL Workflow Advisor