Documentation

Requirements for System Generator Black Box Block Generation

You must have Xilinx^® ISE Design Suite 13.4 or later to generate a System Generator Black Box block.

To verify your System Generator setup, at the command line, enter:

xlVersion

Enable System Generator Black Box Block Generation

Using the GUI

To enable System Generator Black Box block generation using the HDL Workflow Advisor:

1. In the HDL Workflow Advisor, on the left, click Code Generation.

2. In the Advanced tab, select the Generate Xilinx System Generator Black Box option.

3. In the Clocks & Ports tab, set the following fields:

   • For Clock input port, enter clk.

   • For Clock enable input port, enter ce.

   • For Drive clock enable at, select DUT base rate.

Using the Command Line

To enable System Generator Black Box block generation, at the command line, enter:

hdlcfg = coder.config('hdl');
hdlcfg.GenerateXSGBlock = true;
hdlcfg.ClockInputPort = 'clk';
hdlcfg.ClockEnableInputPort = 'ce';
hdlcfg.EnableRate = 'DutBaseRate';

Results of System Generator Black Box Block Generation

After you generate HDL code, you have:

• An XSG subsystem.

• A System Generator Black Box block within the XSG subsystem.

• A System Generator Black Box configuration M-function.

You can use the XSG subsystem in a Simulink^® model, or use the Black Box block and Black Box configuration M-function in a Xilinx System Generator design.

To learn more about generating a System Generator Black Box block, see Using Xilinx System Generator for DSP with HDL Coder.