hdl.BlackBox System object

Package: hdl

Black box for including custom HDL code

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Description

hdl.BlackBox provides a way to include custom HDL code, such as legacy or handwritten HDL code, in a MATLAB® design intended for HDL code generation.

When you create a user-defined System object™ that inherits from hdl.BlackBox, you specify a port interface and simulation behavior that matches your custom HDL code.

HDL Coder™ simulates the design in MATLAB using the behavior you define in the System object. During code generation, instead of generating code for the simulation behavior, the coder instantiates a module with the port interface you specify in the System object.

To use the generated HDL code in a larger system, you include the custom HDL source files with the rest of the generated code.

    Note:   Starting in R2016b, instead of using the step method to perform the operation defined by the System object, you can call the object with arguments, as if it were a function. For example, y = step(obj,x) and y = obj(x) perform equivalent operations.

Construction

B = hdl.BlackBox creates a black box System object for HDL code generation.

Properties

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If 'on', add a clock enable input port to the interface generated for the black box System object. The name of the port is specified by ClockEnableInputPort.

If 'on', add a clock input port to the interface generated for the black box System object. The name of the port is specified by ClockInputPort.

If 'on', add a reset input port to the interface generated for the black box System object. The name of the port is specified by ResetInputPort.

If 'on', allow HDL Coder to move registers across the black box System object, from input to output or output to input.

HDL name for clock enable input port, specified as a character vector.

HDL name for clock input port, specified as a character vector.

VHDL® entity or Verilog® module name generated for the black box System object, specified as a character vector.

Example: 'myBlackBoxName'

Latency of black box System object in clock cycles, specified as an integer.

If 0 or greater, this value is used for delay balancing.

If -1, latency is unknown. This disables delay balancing.

When 'on', generate a VHDL configuration.

When 'off', do not generate a VHDL configuration and require a user-supplied external configuration. Set to 'off' if you are creating your own VHDL configuration.

Number of input pipeline stages, or pipeline depth, to insert in the generated code.

Number of output pipeline stages, or output pipeline depth, to insert in the generated code.

HDL name for reset input port, specified as a character vector.

VHDL architecture name, specified as a character vector. The coder generates the architecture name only if InlineConfigurations is 'on'.

Library from which to load the VHDL component, specified as a character vector.

Number of additional input ports in the custom HDL code, specified as a positive integer.

Number of additional output ports in the custom HDL code, specified as a positive integer.

See Also

Related Examples

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