Documentation

This example shows how to generate a hardware-in-the-loop interface for Speedgoat board programming with Simulink^® Real-Time™ using the Simulink Real-Time FPGA I/O workflow.

To run this example, you must:

• Have a license for Simulink Real-Time software.

• Use Xilinx^® ISE 10.1.

Select a Speedgoat Target Device

Note:   Before selecting a Speedgoat target device, see Third-Party Synthesis Tools and Version Support.

To select a target Speedgoat board:

1. Open the model.

   dxpcSGIO301servo_fpga

   The ServoSystem subsystem is the device under test (DUT) for HDL code generation.

   

2. Right-click the ServoSystem block, and select HDL Code > HDL Workflow Advisor.

3. In the HDL Workflow Advisor, select Set Target > Set Target Device and Synthesis Tool.

4. For Target workflow, select Simulink Real-Time FPGA I/O.

   On the left, the Set Target Interface and Set Target Frequency steps appear under Set Target along with the FPGA Synthesis and Analysis and Download to Target tasks.

5. From the Target platform menu, select the Speedgoat IO301 board.

   Simulink Real-Time and HDL Workflow Advisor support the same set of Speedgoat devices. For a list of supported boards, see Speedgoat FPGA Support.

   

6. Click Run This Task.

   After the Set Target Device and Synthesis Tool task is complete, the HDL Workflow Advisor enables the next task in the hierarchy, Set Target Interface. After the Set Target Device and Synthesis Tool task runs, the HDL Workflow Advisor looks like this figure.

   

Set the Target Interface for Speedgoat Boards

The Set Target Interface task in the HDL Workflow Advisor enables you to define how the inputs and outputs of the DUT map to the inputs and outputs of your Speedgoat target device.

Using the Target Platform Interface and Bit Range / Address / FPGA Pin columns, you can allocate each port on the DUT to an I/O resource on the target device. To allocate ports:

1. In the left pane of the HDL Workflow Advisor, select the Set Target Interface task.

2. In the Target Platform Interface Table, for each port you want to allocate, click the Target Platform Interfaces column and select an I/O resource from the dropdown list. Click Apply.

   This figure shows the Target Platform Interface Table for an example configuration. All ports have been allocated to a PCI Interface address or a single bit on the TTL I/O Connector.

   

   Note:   At least one output port must be allocated to the target device. If all ports are left unallocated, the Set Target Interface task shows an error and terminates. For information about the I/O resource options, refer to the documentation for your target board.

3. Click Run This Task.

4. In the Set Target Frequency task, set your FPGA clock frequency and click Run This Task.

Code Generation, Synthesis, and Generation of Simulink Real-Time Interface Subsystem

After selecting the target device and configuring its port interface, you can enable the HDL Workflow Advisor to perform the next sequence of tasks automatically. These tasks include:

• Prepare Model For HDL Code Generation: Checking the model for HDL code generation compatibility.

• HDL Code Generation: Setting HDL-related options of the Model Configuration Parameters dialog box and generating HDL code.

• FPGA Synthesis and Analysis: Executing synthesis and timing analysis in Xilinx ISE; back annotating the model with critical path information obtained during synthesis.

• Download to Target : Generating an FPGA programming file and a model that contains a Simulink Real-Time interface subsystem.

  Note:   The Download to Target tasks do not actually download anything to a target device. They create an interface subsystem that you can plug into a Simulink Real-Time model.

To run this sequence of tasks automatically:

1. Open the Download to Target task group.

2. Right-click Generate Simulink Real-Time interface and select Run to Selected Task.

3. As the Run to Selected Task sequence executes, the HDL Workflow Advisor displays a progress indicator for each task.

   After the task sequence is complete, you see the Result subpane.

   

4. The Result pane displays a link to a generated model — gm_dxpcSGIO301servo_fpga_slrt. Click the link to open the model.

   

   The model contains the Simulink Real-Time interface subsystem. This new subsystem replaces the DUT (ServoSystem) in the original model. It replaces the internals of the original DUT with a Simulink Real-Time FPGA block and other blocks to work with the algorithm on the FPGA.

5. Save the gm_dxpcSGIO301servo_fpga_slrt model.

6. To learn how to use the generated model with Simulink Real-Time, see FPGA Subsystem Configuration in the Simulink Real-Time documentation.