Description

The Viterbi Decoder block is available with Communications System Toolbox™.

For information about the simulation behavior and block parameters, see Viterbi Decoder.

HDL Coder™ supports the following features of the Viterbi Decoder block:

• Non-recursive encoder/decoder with feed-forward trellis and simple shift register generation configuration

• Sample-based input

• Decoder rates from 1/2 to 1/7

• Constraint length from 3 to 9

HDL Architecture

The Viterbi Decoder block decodes every bit by tracing back through a traceback depth that you define for the block. The block implements a complete traceback for each decision bit, using registers to store the minimum state index and branch decision in the traceback decoding unit. There are two methods to optimize the traceback logic: a pipelined register-based implementation or a RAM-based architecture. See the HDL Code Generation for Viterbi Decoder example.

Register-Based Traceback

You can specify that the traceback decoding unit be pipelined to improve the speed of the generated circuit. You can add pipeline registers to the traceback unit by specifying the number of traceback stages per pipeline register.

Using the TracebackStagesPerPipeline implementation parameter, you can balance the circuit performance based on system requirements. A smaller parameter value indicates the requirement to add more registers to increase the speed of the traceback circuit. Increasing the parameter value results in fewer registers along with a decrease in the circuit speed.

RAM-Based Traceback

Instead of using registers, you can choose to use RAMs to save the survivor branch information. The coder does not support Enable reset input port when using RAM-based traceback.

1. Set the Architecture property of the Viterbi Decoder block to RAM-based Traceback.

   

2. Set the traceback depth on the Viterbi Decoder block mask.

   

RAM-based traceback and register-based traceback differ in the following ways:

• The RAM-based implementation traces back through one set of data to find the initial state to decode the previous set of data. The register-based implementation combines the traceback and decode operations into one step. It uses the best state found from the minimum operation as the decoding initial state.

• RAM-based implementation traces back through M samples, decodes the previous M bits in reverse order, and releases one bit in order at each clock cycle. The register-based implementation decodes one bit after a complete traceback.

Because of the differences in the two traceback algorithms, the RAM-based implementation produces different numerical results than the register-based traceback. A longer traceback depth, for example, 10 times the constraint length, is recommended in the RAM-based traceback. This depth achieves a similar bit error rate (BER) as the register-based implementation. The size of RAM required for the implementation depends on the trellis and the traceback depth.

HDL Block Properties

ConstrainedOutputPipeline

Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.

InputPipeline

Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.

OutputPipeline

Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.

TracebackStagesPerPipeline

See Register-Based Traceback.

Restrictions

• Punctured code: Do not select this option. Punctured code requires frame-based input, which HDL Coder does not support.

• Decision type: The coder does not support the Unquantized decision type.

• Error if quantized input values are out of range: The coder does not support this option.

• Operation mode: The coder supports only the Continuous mode.

• Enable reset input port: When you enable both Enable reset input port and Delay reset action to next time step, HDL support is provided. You must select Continuous operation mode, and use register-based traceback.

• You cannot use the Viterbi Decoder block inside a Resettable Synchronous Subsystem.

Input and Output Data Types

• When Decision type is set to Soft decision, the HDL implementation of the Viterbi Decoder block supports fixed-point inputs and output. For input, the fixed-point data type must be ufixN. N is the number of soft-decision bits. Signed built-in data types (int8, int16, int32) are not supported. For output, the HDL implementation of the Viterbi Decoder block supports block-supported output data types.

• When Decision type is set to Hard decision, the block supports input with data types ufix1 and Boolean. For output, the HDL implementation of the Viterbi Decoder block supports block-supported output data types.

• The HDL implementation of the Viterbi Decoder block does not support double and single input data types. The block does not support floating point output for fixed-point inputs.

Related Examples

• HDL Code Generation for Viterbi Decoder