Add or subtract inputs (HDL Coder)
The Sum of Elements block is available with Simulink®.
For information about the simulation behavior and block parameters, see Sum of Elements.
HDL Coder™ supports Tree and Cascade architectures
for Sum of Elements blocks that have a single vector input with multiple
elements.
This block has multi-cycle implementations that introduce additional latency in the generated code. To see the added latency, view the generated model or validation model. See Generated Model and Validation Model.
| Architecture | Additional cycles of latency | Description |
|---|---|---|
defaultLinear | 0 | Generates a linear chain of adders to compute the sum of products. |
Tree | 0 | Generates a tree structure of adders to compute the sum of products. |
Cascade | 1, when block has a single vector input port. | This implementation optimizes latency * area and is faster
than the |
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
The default Linear implementation
supports complex data.