Multiply-Add

Multiply-add combined operation for HDL Coder

Description

The Multiply-Add block is available with Simulink^®.

For information about the simulation behavior and block parameters, see Multiply-Add block in the Simulink documentation.

Hardware Mapping

To map a combined multiply and add or a multiply and subtract operation to a DSP unit in your target hardware, select the Function setting in the Block Parameters dialog box for the Multiply-Add block.

To map to a DSP unit, specify the SynthesisTool property for your model.

When you generate HDL code for your model, HDL Coder™ configures the multiply-add operation so that your synthesis tool can map to a DSP unit.

Note: Some DSP units do not have the multiply-add capability. To see if your hardware has the multiply-add capability, refer to the documentation for the hardware.

Pipeline Depth

If you have fixed-point inputs to a Multiply-Add block, you can set the PipelineDepth for the block. For floating-point inputs, HDL Coder ignores the PipelineDepth parameter and does not insert the pipeline registers.

The following diagrams show different configurations of pipeline registers for different synthesis tools and PipelineDepth settings. When you specify the PipelineDepth setting, HDL Coder inserts pipeline registers so that the configuration maps efficiently to DSP units.

Altera Hardware with PipelineDepth = 1

Altera Hardware with PipelineDepth = 2

Xilinx Hardware with PipelineDepth = 1

Xilinx Hardware with PipelineDepth = 2

Xilinx Hardware with PipelineDepth = 3

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

PipelineDepth

Number of pipeline stages. The default is auto which means that the coder determines the number of pipeline stages based on your synthesis tool.

You can enter an integer between 0 and 3. For Altera^® hardware targets, the maximum pipeline depth is 2.

Complex Data Support

This block supports code generation for complex signals.

Restrictions

When the block has floating-point inputs, HDL Coder ignores the PipelineDepth parameter and does not insert pipeline registers.
If MaxOversampling = 1 and MaxComputationLatency > 1, you cannot use the resource sharing optimization to share Multiply-Add blocks with nonzero PipelineDepth.
If the block is in a feedback loop and you do not have sufficient delays at the block output, the coder reduces the PipelineDepth to prevent delay balancing failure. For sufficient delays, add Delay blocks at the output of the Multiply-Add block.
To map the combined multiply-add operation to a DSP unit, the width of the third input c has to be less than 64 bits for Altera and 48 bits for Xilinx^® respectively.
The subtraction operation in the Function setting (a.*b)-c does not map to a DSP unit in Altera FPGA libraries.

Documentation