Fast Fourier transform—optimized for HDL code generation (HDL Coder)
The FFT HDL Optimized block is available with DSP System Toolbox™.
For information about the simulation behavior and block parameters, see FFT HDL Optimized.
This block has a single, default HDL architecture.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
If you use the FFT HDL Optimized block with the State Control block inside an Enabled Subsystem, the optional reset port is not supported. If you enable the reset port on the FFT HDL Optimized block in such a subsystem, the model will error on Update Diagram.
You cannot use the FFT HDL Optimized block inside a Resettable Synchronous Subsystem.