Represent subsystem whose execution is enabled by external input (HDL Coder)
An enabled subsystem is a subsystem that receives a control signal via an Enable block. The enabled subsystem executes at each simulation step where the control signal has a positive value.
For detailed information on how to construct and configure enabled subsystems, see Create an Enabled Subsystem in the Simulink® documentation.
When using enabled subsystems in models targeted for HDL code generation, it is good practice to consider the following:
For synthesis results to match Simulink results, the Enable port must be driven by registered logic (with a synchronous clock) on the FPGA.
Put unit delays on Enabled Subsystem output signals. Doing so prevents the code generator from inserting extra bypass registers in the HDL code.
Enabled subsystems can affect synthesis results in the following ways:
In some cases, the system clock speed can drop by a small percentage.
Generated code uses more resources, scaling with the number of enabled subsystem instances and the number of output ports per subsystem.
| Architecture | Description |
|---|---|
Module (default) | Generate code for the subsystem and the blocks within the subsystem. |
BlackBox | Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. This way, you can use a subsystem in your model to generate an interface to existing, manually written HDL code. The black-box interface generation for subsystems is similar to the Model blocks interface generation without the clock signals. |
| Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a "no-op" in the HDL code. |
Automatic pipeline insertion based on the synthesis tool, target
frequency, and multiplier word-lengths. The default is inherit.
See also AdaptivePipelining.
Detects introduction of new delays along one path, and inserts
matching delays on the other paths. The default is inherit.
See also BalanceDelays.
Insert pipeline registers at faster clock rate instead of the
slower data rate. The default is inherit.
See also ClockRatePipelining.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Pipeline register distribution, or register retiming. The default
is off. See also DistributedPipelining.
Synthesis attributes for multiplier mapping. The default is none.
See also DSPStyle.
Remove subsystem hierarchy from generated HDL code. The default
is inherit. See also FlattenHierarchy.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing.
Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See also Streaming.
This block cannot be the DUT, so the block property settings in the Target Specification tab are ignored.
HDL Coder™ supports HDL code generation for enabled subsystems that meet the following conditions:
The enabled subsystem is not the DUT.
The subsystem is not both triggered and enabled.
The enable signal is a scalar.
The data type of the enable signal is either boolean or ufix1.
Outputs of the enabled subsystem have an initial value of 0.
All inputs and outputs of the enabled subsystem (including the enable signal) run at the same rate.
The Show output port parameter
of the Enable block is set to Off.
The States when enabling parameter
of the Enable block is set to held (i.e.,
the Enable block does not reset states when enabled).
The Output when disabled parameter
for the enabled subsystem output ports is set to held (i.e.,
the enabled subsystem does not reset output values when disabled).
If the DUT contains the following blocks, RAMArchitecture is
set to WithClockEnable:
Dual Port RAM
Simple Dual Port RAM
Single Port RAM
The enabled subsystem does not contain the following blocks:
CIC Decimation
CIC Interpolation
FIR Decimation
FIR Interpolation
Downsample
Upsample
HDL Cosimulation blocks for HDL Verifier™
Rate Transition
The Automatic Gain Controller example shows how you can use enabled subsystems in HDL code generation. To open the example, enter:
hdlcoder_agc