Concatenate input signals of same data type to create contiguous output signal (HDL Coder)
The Vector Concatenate block is available with Simulink®.
For information about the simulation behavior and block parameters, see Vector Concatenate.
This block has a single, default HDL architecture.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
This block supports code generation for complex signals.
HDL code generation does not support matrices at the input or output ports of the block .