Delay scalar signal multiple sample periods and output the delayed versions (HDL Coder)
The Tapped Delay block is available with Simulink®.
For information about the simulation behavior and block parameters, see Tapped Delay.
This block has a single, default HDL architecture.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
Suppress reset logic generation. The default is default,
which generates reset logic. See also ResetType.
This block supports code generation for complex signals.