Sum

Add or subtract inputs (HDL Coder)

Description

The Sum block is available with Simulink®.

For information about the simulation behavior and block parameters, see Sum.

HDL Architecture

The default Linear implementation generates a chain of N operations (adders) for N inputs.

HDL Block Properties

ConstrainedOutputPipeline

Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.

InputPipeline

Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.

OutputPipeline

Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.

Complex Data Support

The default Linear implementation supports complex data.

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