Shift bits or binary point of signal (HDL Coder)
The Shift Arithmetic block is available with Simulink®.
For information about the simulation behavior and block parameters, see Shift Arithmetic.
You can generate HDL code when Bits to shift: Source is Dialog or Input port.
The generated VHDL code uses the shift_right function
and sll operator.
The generated Verilog code uses the >>> and <<< shift
operators.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
This block supports code generation for complex signals.
When Bits to shift: Source is Input port, binary point shifting is not supported.