Handle transfer of data between blocks operating at different rates (HDL Coder)
The Rate Transition block is available with Simulink®.
For information about the simulation behavior and block parameters, see Rate Transition.
When the Rate Transition block is operating at a faster input rate and slower output rate, it is good practice to follow the Rate Transition block with a unit delay. Doing so prevents the code generator from inserting an extra bypass register in the HDL code.
See also Multirate Model Requirements for HDL Code Generation.
This block has a single, default HDL architecture.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
Sample rate cannot be 0 or Inf for
block input or output ports.
Ensure data integrity during data transfer must be enabled.
Ensure deterministic data transfer (maximum delay) must be enabled.
This block supports code generation for complex signals.