Generate pseudonoise sequence (HDL Coder)
The PN Sequence Generator block is available with Communications System Toolbox™.
For information about the simulation behavior and block parameters, see PN Sequence Generator.
This block has a single, default HDL architecture.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
You can select Input port as
the Output mask source on the block. However,
in this case, the Mask input signal must be a vector
of data type ufix1.
If you select Reset on nonzero input,
the input to the Rst port must have data type Boolean.
Outputs of type double are not
supported for HDL code generation. All
other output types (including bit packed outputs) are supported.
You cannot use the PN Sequence Generator block inside a Resettable Synchronous Subsystem.