Generate real or complex sinusoidal signals—optimized for HDL code generation (HDL Coder)
The NCO HDL Optimized block is available with DSP System Toolbox™.
For information about the simulation behavior and block parameters, see NCO HDL Optimized.
This block has a single, default HDL architecture.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
The reset type of the lookup table output register. Select none to
synthesize the lookup table to a ROM when your target is an FPGA.
See also LUTRegisterResetType.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
When you set Dither source to Property,
the block adds random dither every cycle. If you generate a validation
model with these settings, a warning is displayed. Random generation
of the internal dither can cause mismatches between the models. You
can increase the error margin for the validation comparison to account
for the difference. You can also disable dither or set Dither
source to Input port to avoid
this issue.
You cannot use the NCO HDL Optimized block inside a Resettable Synchronous Subsystem.