Cosimulate hardware component by communicating with HDL module instance executing in HDL simulator (HDL Coder)
The HDL Cosimulation block is available with HDL Verifier™.
For information about the simulation behavior and block parameters, see HDL Cosimulation.
HDL Coder™ supports HDL code generation for the following HDL Cosimulation blocks:
HDL Verifier for use with Mentor Graphics® ModelSim®
HDL Verifier for use with Cadence Incisive®
Each of the HDL Cosimulation blocks cosimulates a hardware component by applying input signals to, and reading output signals from, an HDL model that executes under an HDL simulator.
For information about timing, latency, data typing, frame-based processing, and other issues when setting up an HDL cosimulation, see the Define HDL Cosimulation Block Interface section of the HDL Verifier documentation.
You can use an HDL Cosimulation block with HDL Coder to generate an interface to your manually written or legacy HDL code. When an HDL Cosimulation block is included in a model, the coder generates a VHDL® or Verilog® interface, depending on the selected target language.
When the target language is VHDL, the generated interface includes:
An entity definition. The entity defines ports (input, output, and clock) corresponding in name and data type to the ports configured on the HDL Cosimulation block. Clock enable and reset ports are also declared.
An RTL architecture including a component declaration, a component configuration declaring signals corresponding to signals connected to the HDL Cosimulation ports, and a component instantiation.
Port assignment statements as required by the model.
When the target language is Verilog, the generated interface includes:
A module defining ports (input, output, and clock)
corresponding in name and data type to the ports configured on the HDL
Cosimulation block. The module also defines clock enable and
reset ports, and wire declarations corresponding
to signals connected to the HDL Cosimulation ports.
A module instance.
Port assignment statements as required by the model.
Before initiating code generation, to check the requirements for using the HDL Cosimulation block for code generation, select Simulation > Update Diagram.
This block has a single, default HDL architecture.
For implementation parameter descriptions, see Customize Black Box or HDL Cosimulation Interface.