addClockInterface('ClockConnection',clock_port,'ResetConnection',reset_port)
addClockInterface('ClockConnection',clock_port,'ResetConnection',reset_port,Name,Value)
addClockInterface('ClockConnection', adds
a clock and reset interface to an clock_port,'ResetConnection',reset_port)hdlcoder.ReferenceDesign object.
addClockInterface('ClockConnection', adds
a clock and reset interface to the clock_port,'ResetConnection',reset_port,Name,Value)hdlcoder.ReferenceDesign object
with additional options specified by one or more Name,Value pair
arguments.
You must run this method before running the hdlcoder.ReferenceDesign.addClockInterface method.
Specify optional comma-separated pairs of Name,Value arguments.
Name is the argument
name and Value is the corresponding
value. Name must appear
inside single quotes (' ').
You can specify several name and value pair
arguments in any order as Name1,Value1,...,NameN,ValueN.
'DefaultFrequencyMHz' — The default frequency in MHz0 (default) | integerThe default clock frequency in MHz of the clock module IP in the reference design, specified as an integer. When you open the HDL Workflow Advisor, HDL Coder™ populates this information for Default (MHz) in the Set Target Frequency task.
Example: 'DefaultFrequencyMHz', 50 specifies
the default frequency as 50 MHz.
'MinFrequencyMHz' — The minimum frequency in MHz0 (default) | integerThe minimum clock frequency in MHz of the clock module IP in the reference design, specified as an integer.
Example: 'MinFrequencyMHz', 5 specifies the
minimum clock frequency as 5 MHz.
'MaxFrequencyMHz' — The maximum frequency in MHz0 (default) | integerThe maximum clock frequency in MHz of the clock module IP in
the reference design, specified as an integer. In the HDL Workflow
Advisor, HDL Coder sets the Frequency Range (MHz) in
the Set Target Frequency task based on the MinFrequencyMHz and MaxFrequencyMHz values
that you specify.
Example: 'MaxFrequencyMHz', 500 specifies
the maximum clock frequency as 500 MHz.
'ClockNumber' — Clock output port number1 (default) | integerPort number of the clock output from the clock module IP, specified as an integer.
Example: 'ClockNumber', 2 specifies to use
the second output port in the clock module IP as the clock port.
'ClockModuleInstance' — Clock module name'clk_wiz_0' (default) | character vectorThe name of the clock module in the reference design, specified as a character vector.
Example: 'ClockModuleInstance', 'clk_wiz_1' specifies clk_wiz_1 as
the name of the clocking wizard IP.
hdlcoder.ReferenceDesign | hdlcoder.ReferenceDesign.addAXI4SlaveInterface