Package: hdl
Single, simple dual, or dual-port RAM for memory read/write access
hdl.RAM
reads from and writes to memory locations
for a single, simple dual, or dual-port RAM. The output data is delayed
one step.
If your data is scalar, HDL Coder™ infers a single RAM block. If your data is a vector, HDL Coder infers an array of parallel RAM banks.
Note:
Starting in R2016b, instead of using the |
If your data is scalar, the RAM size, or number of locations, is inferred from the data type of the address variable.
Data type of address variable | RAM address size (bits) |
---|---|
single or double | 16 |
uint | N |
embedded.fi | WordLength |
The maximum RAM address size is 32 bits.
If your data is a vector, HDL Coder generates an array of parallel RAM banks. The number of elements in the vector determines the number of RAM banks.
The size of each RAM bank is inferred from the data type of the address variable.
Data type of address variable | RAM address size (bits) |
---|---|
single or double | 16 |
uint | N |
embedded.fi | WordLength |
The maximum RAM bank address size is 32 bits.
H = hdl.RAM
creates a single port RAM System
object. This object allows you to read from or write to a memory location.
The output data port corresponds to the read/write address passed
in with the step method.
H = hdl.RAM(Name,Value)
creates a single,
simple dual, or dual port hdl.RAM
System object, H
,
with each specified property Name set to the specified Value. You
can specify additional name-value pair arguments in any
order as (Name1,Value1,...,NameN,ValueN)
. For the
list of available property names, see Properties.
|
Type of RAM Default: Specify the type of RAM. Values of this property are listed in the table.
| ||||||
|
Behavior for Write output Default: Specify the behavior for Write output for single-port and dual-port RAMs. Values of this property are listed in the table.
|
step | Read or write input value to memory location |