hdl.RAM System object

Package: hdl

Single, simple dual, or dual-port RAM for memory read/write access

Description

hdl.RAM reads from and writes to memory locations for a single, simple dual, or dual-port RAM. The output data is delayed one step.

If your data is scalar, HDL Coder™ infers a single RAM block. If your data is a vector, HDL Coder infers an array of parallel RAM banks.

    Note:   Starting in R2016b, instead of using the step method to perform the operation defined by the System object™, you can call the object with arguments, as if it were a function. For example, y = step(obj,x) and y = obj(x) perform equivalent operations.

RAM Inference with Scalar Data

If your data is scalar, the RAM size, or number of locations, is inferred from the data type of the address variable.

Data type of address variableRAM address size (bits)
single or double16
uintNN
embedded.fiWordLength

The maximum RAM address size is 32 bits.

RAM Inference with Vector Data

If your data is a vector, HDL Coder generates an array of parallel RAM banks. The number of elements in the vector determines the number of RAM banks.

The size of each RAM bank is inferred from the data type of the address variable.

Data type of address variableRAM address size (bits)
single or double16
uintNN
embedded.fiWordLength

The maximum RAM bank address size is 32 bits.

Construction

H = hdl.RAM creates a single port RAM System object. This object allows you to read from or write to a memory location. The output data port corresponds to the read/write address passed in with the step method.

H = hdl.RAM(Name,Value) creates a single, simple dual, or dual port hdl.RAM System object, H, with each specified property Name set to the specified Value. You can specify additional name-value pair arguments in any order as (Name1,Value1,...,NameN,ValueN). For the list of available property names, see Properties.

Properties

RAMType

Type of RAM

Default: Single port

Specify the type of RAM. Values of this property are listed in the table.

Single Port

Create a single port RAM, with three inputs and one output.

Inputs:

  • Write Data

  • Address

  • Write enable

Output: Read data

Simple dual port

Create a simple dual-port RAM, with four inputs and one output.

Inputs:

  • Write Data

  • Write address

  • Write enable

  • Read address

Output: Output data from read address

Dual port

Create a dual-port RAM, with four inputs and two outputs.

Inputs:

  • Write Data

  • Write address

  • Write enable

  • Read address

Outputs:

  • Output data from write address

  • Output data from read address

WriteOutputValue

Behavior for Write output

Default: New data

Specify the behavior for Write output for single-port and dual-port RAMs. Values of this property are listed in the table.

New data

Send out new data at the address to the output.

Old data

Send out old data at the address to the output.

Methods

stepRead or write input value to memory location

Examples

expand all

Construct System object to read from or write to a memory location in RAM.

The output data port corresponds to the read/write address passed in. During a write operation, the old data at the write address is sent out as the output.

 H = hdl.RAM('RAMType','Single port','WriteOutputValue','Old data')
H = 

  hdl.RAM with properties:

             RAMType: 'Single port'
    WriteOutputValue: 'Old data'

Construct System object to read from and write to different memory locations in RAM.

The output data port corresponds to the read address. If a read operation is performed at the same address as the write operation, old data at that address is read out as the output.

H = hdl.RAM('RAMType','Simple dual port')
H = 

  hdl.RAM with properties:

    RAMType: 'Simple dual port'

Construct System object to read from and write to different memory locations in RAM.

There are two output ports, a write output data port and a read output data port. The write output data port sends out the new data at the write address. The read output data port sends out the old data at the read address.

H = hdl.RAM('RAMType','Dual port','WriteOutputValue','New data')
H = 

  hdl.RAM with properties:

             RAMType: 'Dual port'
    WriteOutputValue: 'New data'

Create System object that writes to a single port RAM and reads the newly written value.

Construct single-port RAM System object.

hRAM = hdl.RAM('RAMType','Single port','WriteOutputValue','New data');

Preallocate memory.

dataLength    = 100;
[dataIn dataOut] = deal(zeros(1,dataLength));

Write randomly generated data to the System object, and then read data back out again.

for ii = 1:dataLength
  dataIn(ii)  = randi([0 63],1,1,'uint8');
  addressIn   = uint8(ii-1);
  writeEnable = true;
  dataOut(ii) = step(hRAM,dataIn(ii),addressIn,writeEnable);
end ;
Was this topic helpful?