Morphological open of grayscale pixel data (HDL Coder)
The Grayscale Opening block is available with Vision HDL Toolbox™.
For information about the simulation behavior and block parameters, see Grayscale Opening.
This block has a single, default HDL architecture.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
You cannot use the Grayscale Opening block inside a Resettable Synchronous Subsystem.