Multiply input by constant (HDL Coder)
The Gain block is available with Simulink®.
For information about the simulation behavior and block parameters, see Gain.
You can use a tunable parameter in a Gain block intended for HDL code generation. For details, see Generate DUT Ports for Tunable Parameters.
ConstMultiplierOptimization | Description |
|---|---|
none(Default) | By default, HDL Coder™ does not perform CSD or FCSD optimizations. Code generated for the Gain block retains multiplier operations. |
csd | When you specify this option, the generated code decreases the area used by the model while maintaining or increasing clock speed, using canonical signed digit (CSD) techniques. CSD replaces multiplier operations with add and subtract operations. CSD minimizes the number of addition operations required for constant multiplication by representing binary numbers with a minimum count of nonzero digits. |
fcsd | This option uses factored CSD (FCSD) techniques, which replace multiplier operations with shift and add/subtract operations on certain factors of the operands. These factors are generally prime but can also be a number close to a power of 2, which favors area reduction. You can achieve a greater area reduction with FCSD at the cost of decreasing clock speed. |
auto | When you specify this option, the coder chooses between
the CSD or FCSD optimizations. The coder chooses the optimization
that yields the most area-efficient implementation, based on the number
of adders required. When you specify |
Canonical signed digit (CSD) or factored CSD optimization. The
default is none. See also ConstMultiplierOptimization.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Synthesis attributes for multiplier mapping. The default is none.
See also DSPStyle.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
This block supports code generation for complex signals.