Generate enumerated constant value (HDL Coder)
The Enumerated Constant block is available with Simulink®.
For information about the simulation behavior and block parameters, see Enumerated Constant.
This block has a single, default HDL architecture.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.