Perform discrete-time integration or accumulation of signal (HDL Coder)
The Discrete-Time Integrator block is available with Simulink®.
For information about the simulation behavior and block parameters, see Discrete-Time Integrator.
This block has a single, default HDL architecture.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
State ports are not supported for HDL code generation. Clear the Show state port option.
External initial conditions are not supported for
HDL code generation. Set Initial condition source to Internal.
Width of input and output signals must not exceed 32 bits.