Description

The Discrete PID Controller block is available with Simulink^®.

For information about the simulation behavior and block parameters, see Discrete PID Controller.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline

Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.

InputPipeline

Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.

OutputPipeline

Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.

Restrictions

HDL code generation does not support the following settings:

• Continuous-time.

• Filter method > Backward Euler or Trapezoidal.

• Source > external.

• External reset > rising, falling, either, or level.

• If inputs are of type Double, Anti-windup method > clamping.