Delay input signal by fixed or variable sample periods (HDL Coder)
The Delay block is available with Simulink®. For information about simulation behavior and block parameters, see Delay.
| Block Parameter Setting | Description |
|---|---|
Set External reset to Level . | Generates a reset port in the HDL code. |
| Select Show enable port. | Generates an enable port in the HDL code. |
For Initial condition, set Source to Dialog and
enter the value. | Specifies an initial condition for the block. |
Set Input processing to Columns
as channels (frame based). | Expects vector input data, where each element of the vector represents a sample in time. |
If you use a State Control block with the Delay block inside a subsystem in your Simulink model, use these additional settings.
| Block Parameter Setting | Description |
|---|---|
Set External reset to Level
hold for Synchronous mode
and Level for Classic mode
of the State Control block. | Generates a reset port in the HDL code. |
| Set Delay length to zero for a Delay block with an external enable port. | Treated as a wire in only Synchronous mode
of the State Control block. |
| Set Delay length to zero for a Delay block with an external reset port. | Treated as a wire in Synchronous and Classic modes
of the State Control block. |
For more information about the State Control block, see State Control.
This block has a single, default HDL architecture.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
Suppress reset logic generation. The default is default,
which generates reset logic. See also ResetType.
Map delays to RAM instead of registers. The default is off.
See also UseRAM.
This block supports code generation for complex signals.
For Initial condition and Delay
length, Source set to Input
port is not supported for HDL code generation.