Create convolutional code from binary data (HDL Coder)
The Convolutional Encoder block is available with Communications System Toolbox™.
For information about the simulation behavior and block parameters, see Convolutional Encoder.
This block has a single, default HDL architecture.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
Input data requirements:
Must be sample-based,
Must have a boolean or ufix1 data
type.
HDL Coder™ supports only the following coding rates:
½ to 1/7
2/3
The coder supports only constraint lengths for 3 to 9.
Specify Trellis structure by
the poly2trellis function.
The coder supports the following Operation mode settings:
Continuous
Reset on nonzero input via port
If you select this mode, you must select the Delay reset action to next time step option. When you select this option, the Convolutional Encoder block finishes its current computation before executing a reset.
You cannot use the Convolutional Encoder block inside a Resettable Synchronous Subsystem.