Generate constant value (HDL Coder)
The Constant block is available with Simulink®.
For information about the simulation behavior and block parameters, see Constant.
You can use a tunable parameter in a Constant block intended for HDL code generation. For details, see Generate DUT Ports for Tunable Parameters.
| Architecture | Parameters | Description |
|---|---|---|
defaultConstant | None | This implementation emits the value of the Constant block. |
Logic Value | None | By default, this implementation emits the character 'Z' for
each bit in the signal. For example, for a 4-bit signal, the implementation
would emit 'ZZZZ'. |
{'Value', 'Z'} | If the signal is in a high-impedance state, use this parameter
value. This implementation emits the character 'Z' for
each bit in the signal. For example, for a 4-bit signal, the implementation
would emit 'ZZZZ'. | |
{'Value', 'X'} | If the signal is in an unknown state, use this parameter value.
This implementation emits the character 'X' for
each bit in the signal. For example, for a 4-bit signal, the implementation
would emit 'XXXX'. |
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
This block supports code generation for complex signals.
The Logic Value implementation
does not support the double data type. If you specify
this implementation for a constant value of type double,
a code generation error occurs.
For Sample time, enter -1. Delay
balancing does not support an inf sample time.
When Output data type is a bus object, Constant value cannot be 0.