Select signals from incoming bus (HDL Coder)
The Bus Selector block is available with Simulink®.
For information about the simulation behavior and block parameters, see Bus Selector.
This block has a single, default HDL architecture.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
You must set the Simulation > Configuration Parameters > Diagnostics > Connectivity + Mux blocks used to
create bus signals parameter to error.
For details, see Prevent Bus and Mux Mixtures.
Inputs must be bus signals. Non-bus inputs are not supported for code generation.