Bus Creator
Create signal bus (HDL Coder)
Description
The Bus Creator block is available with Simulink®.
For information about the simulation behavior and block parameters, see Bus Creator.
HDL Architecture
This block has a single, default HDL architecture.
HDL Block Properties
- ConstrainedOutputPipeline
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
- InputPipeline
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
- OutputPipeline
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
Restrictions
Setup
Set the Simulation > Configuration Parameters > Diagnostics > Connectivity + Mux blocks used to create bus signals parameter to
error. For details, see Prevent Bus and Mux Mixtures.For Output data type, specify a bus object.
