Resample input at higher rate by repeating values (HDL Coder)
The Repeat block is available with DSP System Toolbox™.
For information about the simulation behavior and block parameters, see Repeat.
The Repeat block uses fewer hardware resources than the Upsample block. If your algorithm does not require zero-padding upsampling, use the Repeat block.
This block has a single, default HDL architecture.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.
For Frame based mode, select Maintain
input frame size. When the Upsample block is in this
mode, Initial conditions has no
effect on generated code.