Upsample, filter, and downsample input signals—optimized for HDL code generation (HDL Coder)
The FIR Rate Conversion HDL Optimized block is available with DSP System Toolbox™.
For information about the simulation behavior and block parameters, see FIR Rate Conversion HDL Optimized.
This block has a single, default HDL architecture.
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See also ConstrainedOutputPipeline.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline.
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline.